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Revert "[DAGCombiner] Teach scalarizeBinOpOfSplats handle scalable splat." 

This reverts commit 58dfaaaace.

Massive AARCH test failures in buildbot.
This commit is contained in:
Max Kazantsev 2022-07-19 13:26:31 +07:00
parent e01bf5a3e2
commit 69b284aaf6
7 changed files with 19 additions and 32 deletions
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8
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -23466,14 +23466,10 @@ static SDValue scalarizeBinOpOfSplats(SDNode *N, SelectionDAG &DAG,
int Index0, Index1;
SDValue Src0 = DAG.getSplatSourceVector(N0, Index0);
SDValue Src1 = DAG.getSplatSourceVector(N1, Index1);
// Extract element from splat_vector should be free.
// TODO: use DAG.isSplatValue instead?
bool IsBothSplatVector = N0.getOpcode() == ISD::SPLAT_VECTOR &&
N1.getOpcode() == ISD::SPLAT_VECTOR;
if (!Src0 || !Src1 || Index0 != Index1 ||
Src0.getValueType().getVectorElementType() != EltVT ||
Src1.getValueType().getVectorElementType() != EltVT ||
!(IsBothSplatVector || TLI.isExtractVecEltCheap(VT, Index0)) ||
!TLI.isExtractVecEltCheap(VT, Index0) ||
!TLI.isOperationLegalOrCustom(Opcode, EltVT))
return SDValue();
@ -23495,8 +23491,6 @@ static SDValue scalarizeBinOpOfSplats(SDNode *N, SelectionDAG &DAG,
}
// bo (splat X, Index), (splat Y, Index) --> splat (bo X, Y), Index
if (VT.isScalableVector())
return DAG.getSplatVector(VT, DL, ScalarBO);
SmallVector<SDValue, 8> Ops(VT.getVectorNumElements(), ScalarBO);
return DAG.getBuildVector(VT, DL, Ops);
}

4
llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll
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@ -879,9 +879,9 @@ define <vscale x 8 x i64> @vadd_xx_nxv8i64(i64 %a, i64 %b) nounwind {
;
; RV64-LABEL: vadd_xx_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: add a0, a0, a1
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vmv.v.x v8, a0
; RV64-NEXT: vadd.vx v8, v8, a1
; RV64-NEXT: ret
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer

4
llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll
View File

@ -1370,9 +1370,9 @@ define <vscale x 8 x i64> @vand_xx_nxv8i64(i64 %a, i64 %b) nounwind {
;
; RV64-LABEL: vand_xx_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: and a0, a0, a1
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vmv.v.x v8, a0
; RV64-NEXT: vand.vx v8, v8, a1
; RV64-NEXT: ret
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer

23
llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll
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@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64NOM
; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
; RUN: llc -mtriple=riscv32 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,RV64M
; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
define <vscale x 1 x i8> @vmul_vv_nxv1i8(<vscale x 1 x i8> %va, <vscale x 1 x i8> %vb) {
; CHECK-LABEL: vmul_vv_nxv1i8:
@ -939,19 +939,12 @@ define <vscale x 8 x i64> @vmul_xx_nxv8i64(i64 %a, i64 %b) nounwind {
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
; RV64NOM-LABEL: vmul_xx_nxv8i64:
; RV64NOM: # %bb.0:
; RV64NOM-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64NOM-NEXT: vmv.v.x v8, a0
; RV64NOM-NEXT: vmul.vx v8, v8, a1
; RV64NOM-NEXT: ret
;
; RV64M-LABEL: vmul_xx_nxv8i64:
; RV64M: # %bb.0:
; RV64M-NEXT: mul a0, a0, a1
; RV64M-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64M-NEXT: vmv.v.x v8, a0
; RV64M-NEXT: ret
; RV64-LABEL: vmul_xx_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vmv.v.x v8, a0
; RV64-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: ret
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%head2 = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0

4
llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll
View File

@ -1163,9 +1163,9 @@ define <vscale x 8 x i64> @vor_xx_nxv8i64(i64 %a, i64 %b) nounwind {
;
; RV64-LABEL: vor_xx_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: or a0, a0, a1
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vmv.v.x v8, a0
; RV64-NEXT: vor.vx v8, v8, a1
; RV64-NEXT: ret
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer

4
llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll
View File

@ -857,9 +857,9 @@ define <vscale x 8 x i64> @vsub_xx_nxv8i64(i64 %a, i64 %b) nounwind {
;
; RV64-LABEL: vsub_xx_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: sub a0, a0, a1
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vmv.v.x v8, a0
; RV64-NEXT: vsub.vx v8, v8, a1
; RV64-NEXT: ret
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer

4
llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
View File

@ -1370,9 +1370,9 @@ define <vscale x 8 x i64> @vxor_xx_nxv8i64(i64 %a, i64 %b) nounwind {
;
; RV64-LABEL: vxor_xx_nxv8i64:
; RV64: # %bb.0:
; RV64-NEXT: xor a0, a0, a1
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, mu
; RV64-NEXT: vsetvli a2, zero, e64, m8, ta, mu
; RV64-NEXT: vmv.v.x v8, a0
; RV64-NEXT: vxor.vx v8, v8, a1
; RV64-NEXT: ret
%head1 = insertelement <vscale x 8 x i64> poison, i64 %a, i32 0
%splat1 = shufflevector <vscale x 8 x i64> %head1, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer