forked from OSchip/llvm-project
[NVPTX] Upgrade NVVM intrinsics in InstCombineCalls.
Summary: There are many NVVM intrinsics that we can't entirely get rid of, but that nonetheless often correspond to target-generic LLVM intrinsics. For example, if flush denormals to zero (ftz) is enabled, we can convert @llvm.nvvm.ceil.ftz.f to @llvm.ceil.f32. On the other hand, if ftz is disabled, we can't do this, because @llvm.ceil.f32 will be lowered to a non-ftz PTX instruction. In this case, we can, however, simplify the non-ftz nvvm ceil intrinsic, @llvm.nvvm.ceil.f, to @llvm.ceil.f32. These transformations are particularly useful because they let us constant fold instructions that appear in libdevice, the bitcode library that ships with CUDA and essentially functions as its libm. Reviewers: tra Subscribers: hfinkel, majnemer, llvm-commits Differential Revision: https://reviews.llvm.org/D28794 llvm-svn: 293244
This commit is contained in:
Justin Lebar
parent
322c127bee
commit
698c31b8db
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@ -1498,6 +1498,253 @@ static bool removeTriviallyEmptyRange(IntrinsicInst &I, unsigned StartID,
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return false;
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return false;
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}
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}
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// Convert NVVM intrinsics to target-generic LLVM code where possible.
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static Instruction *SimplifyNVVMIntrinsic(IntrinsicInst *II, InstCombiner &IC) {
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// Each NVVM intrinsic we can simplify can be replaced with one of:
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//
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// * an LLVM intrinsic,
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// * an LLVM cast operation,
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// * an LLVM binary operation, or
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// * ad-hoc LLVM IR for the particular operation.
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// Some transformations are only valid when the module's
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// flush-denormals-to-zero (ftz) setting is true/false, whereas other
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// transformations are valid regardless of the module's ftz setting.
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enum FtzRequirementTy {
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FTZ_Any, // Any ftz setting is ok.
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FTZ_MustBeOn, // Transformation is valid only if ftz is on.
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FTZ_MustBeOff, // Transformation is valid only if ftz is off.
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};
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// Classes of NVVM intrinsics that can't be replaced one-to-one with a
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// target-generic intrinsic, cast op, or binary op but that we can nonetheless
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// simplify.
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enum SpecialCase {
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SPC_Reciprocal,
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};
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// SimplifyAction is a poor-man's variant (plus an additional flag) that
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// represents how to replace an NVVM intrinsic with target-generic LLVM IR.
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struct SimplifyAction {
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// Invariant: At most one of these Optionals has a value.
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Optional<Intrinsic::ID> IID;
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Optional<Instruction::CastOps> CastOp;
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Optional<Instruction::BinaryOps> BinaryOp;
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Optional<SpecialCase> Special;
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FtzRequirementTy FtzRequirement = FTZ_Any;
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SimplifyAction() = default;
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SimplifyAction(Intrinsic::ID IID, FtzRequirementTy FtzReq)
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: IID(IID), FtzRequirement(FtzReq) {}
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// Cast operations don't have anything to do with FTZ, so we skip that
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// argument.
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SimplifyAction(Instruction::CastOps CastOp) : CastOp(CastOp) {}
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SimplifyAction(Instruction::BinaryOps BinaryOp, FtzRequirementTy FtzReq)
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: BinaryOp(BinaryOp), FtzRequirement(FtzReq) {}
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SimplifyAction(SpecialCase Special, FtzRequirementTy FtzReq)
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: Special(Special), FtzRequirement(FtzReq) {}
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};
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// Try to generate a SimplifyAction describing how to replace our
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// IntrinsicInstr with target-generic LLVM IR.
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const SimplifyAction Action = [II]() -> SimplifyAction {
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switch (II->getIntrinsicID()) {
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// NVVM intrinsics that map directly to LLVM intrinsics.
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case Intrinsic::nvvm_ceil_d:
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return {Intrinsic::ceil, FTZ_Any};
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case Intrinsic::nvvm_ceil_f:
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return {Intrinsic::ceil, FTZ_MustBeOff};
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case Intrinsic::nvvm_ceil_ftz_f:
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return {Intrinsic::ceil, FTZ_MustBeOn};
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case Intrinsic::nvvm_fabs_d:
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return {Intrinsic::fabs, FTZ_Any};
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case Intrinsic::nvvm_fabs_f:
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return {Intrinsic::fabs, FTZ_MustBeOff};
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case Intrinsic::nvvm_fabs_ftz_f:
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return {Intrinsic::fabs, FTZ_MustBeOn};
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case Intrinsic::nvvm_floor_d:
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return {Intrinsic::floor, FTZ_Any};
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case Intrinsic::nvvm_floor_f:
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return {Intrinsic::floor, FTZ_MustBeOff};
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case Intrinsic::nvvm_floor_ftz_f:
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return {Intrinsic::floor, FTZ_MustBeOn};
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case Intrinsic::nvvm_fma_rn_d:
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return {Intrinsic::fma, FTZ_Any};
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case Intrinsic::nvvm_fma_rn_f:
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return {Intrinsic::fma, FTZ_MustBeOff};
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case Intrinsic::nvvm_fma_rn_ftz_f:
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return {Intrinsic::fma, FTZ_MustBeOn};
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case Intrinsic::nvvm_fmax_d:
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return {Intrinsic::maxnum, FTZ_Any};
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case Intrinsic::nvvm_fmax_f:
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return {Intrinsic::maxnum, FTZ_MustBeOff};
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case Intrinsic::nvvm_fmax_ftz_f:
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return {Intrinsic::maxnum, FTZ_MustBeOn};
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case Intrinsic::nvvm_fmin_d:
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return {Intrinsic::minnum, FTZ_Any};
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case Intrinsic::nvvm_fmin_f:
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return {Intrinsic::minnum, FTZ_MustBeOff};
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case Intrinsic::nvvm_fmin_ftz_f:
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return {Intrinsic::minnum, FTZ_MustBeOn};
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case Intrinsic::nvvm_round_d:
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return {Intrinsic::round, FTZ_Any};
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case Intrinsic::nvvm_round_f:
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return {Intrinsic::round, FTZ_MustBeOff};
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case Intrinsic::nvvm_round_ftz_f:
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return {Intrinsic::round, FTZ_MustBeOn};
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case Intrinsic::nvvm_sqrt_rn_d:
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return {Intrinsic::sqrt, FTZ_Any};
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case Intrinsic::nvvm_sqrt_f:
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// nvvm_sqrt_f is a special case. For most intrinsics, foo_ftz_f is the
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// ftz version, and foo_f is the non-ftz version. But nvvm_sqrt_f adopts
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// the ftz-ness of the surrounding code. sqrt_rn_f and sqrt_rn_ftz_f are
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// the versions with explicit ftz-ness.
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return {Intrinsic::sqrt, FTZ_Any};
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case Intrinsic::nvvm_sqrt_rn_f:
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return {Intrinsic::sqrt, FTZ_MustBeOff};
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case Intrinsic::nvvm_sqrt_rn_ftz_f:
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return {Intrinsic::sqrt, FTZ_MustBeOn};
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case Intrinsic::nvvm_trunc_d:
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return {Intrinsic::trunc, FTZ_Any};
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case Intrinsic::nvvm_trunc_f:
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return {Intrinsic::trunc, FTZ_MustBeOff};
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case Intrinsic::nvvm_trunc_ftz_f:
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return {Intrinsic::trunc, FTZ_MustBeOn};
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// NVVM intrinsics that map to LLVM cast operations.
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//
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// Note that llvm's target-generic conversion operators correspond to the rz
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// (round to zero) versions of the nvvm conversion intrinsics, even though
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// most everything else here uses the rn (round to nearest even) nvvm ops.
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case Intrinsic::nvvm_d2i_rz:
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case Intrinsic::nvvm_f2i_rz:
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case Intrinsic::nvvm_d2ll_rz:
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case Intrinsic::nvvm_f2ll_rz:
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return {Instruction::FPToSI};
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case Intrinsic::nvvm_d2ui_rz:
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case Intrinsic::nvvm_f2ui_rz:
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case Intrinsic::nvvm_d2ull_rz:
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case Intrinsic::nvvm_f2ull_rz:
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return {Instruction::FPToUI};
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case Intrinsic::nvvm_i2d_rz:
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case Intrinsic::nvvm_i2f_rz:
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case Intrinsic::nvvm_ll2d_rz:
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case Intrinsic::nvvm_ll2f_rz:
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return {Instruction::SIToFP};
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case Intrinsic::nvvm_ui2d_rz:
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case Intrinsic::nvvm_ui2f_rz:
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case Intrinsic::nvvm_ull2d_rz:
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case Intrinsic::nvvm_ull2f_rz:
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return {Instruction::UIToFP};
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// NVVM intrinsics that map to LLVM binary ops.
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case Intrinsic::nvvm_add_rn_d:
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return {Instruction::FAdd, FTZ_Any};
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case Intrinsic::nvvm_add_rn_f:
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return {Instruction::FAdd, FTZ_MustBeOff};
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case Intrinsic::nvvm_add_rn_ftz_f:
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return {Instruction::FAdd, FTZ_MustBeOn};
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case Intrinsic::nvvm_mul_rn_d:
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return {Instruction::FMul, FTZ_Any};
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case Intrinsic::nvvm_mul_rn_f:
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return {Instruction::FMul, FTZ_MustBeOff};
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case Intrinsic::nvvm_mul_rn_ftz_f:
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return {Instruction::FMul, FTZ_MustBeOn};
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case Intrinsic::nvvm_div_rn_d:
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return {Instruction::FDiv, FTZ_Any};
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case Intrinsic::nvvm_div_rn_f:
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return {Instruction::FDiv, FTZ_MustBeOff};
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case Intrinsic::nvvm_div_rn_ftz_f:
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return {Instruction::FDiv, FTZ_MustBeOn};
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// The remainder of cases are NVVM intrinsics that map to LLVM idioms, but
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// need special handling.
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//
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// We seem to be mising intrinsics for rcp.approx.{ftz.}f32, which is just
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// as well.
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case Intrinsic::nvvm_rcp_rn_d:
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return {SPC_Reciprocal, FTZ_Any};
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case Intrinsic::nvvm_rcp_rn_f:
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return {SPC_Reciprocal, FTZ_MustBeOff};
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case Intrinsic::nvvm_rcp_rn_ftz_f:
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return {SPC_Reciprocal, FTZ_MustBeOn};
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// We do not currently simplify intrinsics that give an approximate answer.
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// These include:
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//
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// - nvvm_cos_approx_{f,ftz_f}
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// - nvvm_ex2_approx_{d,f,ftz_f}
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// - nvvm_lg2_approx_{d,f,ftz_f}
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// - nvvm_sin_approx_{f,ftz_f}
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// - nvvm_sqrt_approx_{f,ftz_f}
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// - nvvm_rsqrt_approx_{d,f,ftz_f}
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// - nvvm_div_approx_{ftz_d,ftz_f,f}
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// - nvvm_rcp_approx_ftz_d
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//
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// Ideally we'd encode them as e.g. "fast call @llvm.cos", where "fast"
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// means that fastmath is enabled in the intrinsic. Unfortunately only
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// binary operators (currently) have a fastmath bit in SelectionDAG, so this
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// information gets lost and we can't select on it.
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//
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// TODO: div and rcp are lowered to a binary op, so these we could in theory
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// lower them to "fast fdiv".
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default:
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return {};
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}
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}();
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// If Action.FtzRequirementTy is not satisfied by the module's ftz state, we
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// can bail out now. (Notice that in the case that IID is not an NVVM
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// intrinsic, we don't have to look up any module metadata, as
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// FtzRequirementTy will be FTZ_Any.)
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if (Action.FtzRequirement != FTZ_Any) {
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bool FtzEnabled =
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II->getFunction()->getFnAttribute("nvptx-f32ftz").getValueAsString() ==
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"true";
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if (FtzEnabled != (Action.FtzRequirement == FTZ_MustBeOn))
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return nullptr;
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}
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// Simplify to target-generic intrinsic.
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if (Action.IID) {
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SmallVector<Value *, 4> Args(II->arg_operands());
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// All the target-generic intrinsics currently of interest to us have one
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// type argument, equal to that of the nvvm intrinsic's argument.
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ArrayRef<Type *> Tys = {II->getArgOperand(0)->getType()};
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return CallInst::Create(
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Intrinsic::getDeclaration(II->getModule(), *Action.IID, Tys), Args);
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}
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// Simplify to target-generic binary op.
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if (Action.BinaryOp)
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return BinaryOperator::Create(*Action.BinaryOp, II->getArgOperand(0),
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II->getArgOperand(1), II->getName());
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// Simplify to target-generic cast op.
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if (Action.CastOp)
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return CastInst::Create(*Action.CastOp, II->getArgOperand(0), II->getType(),
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II->getName());
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// All that's left are the special cases.
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if (!Action.Special)
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return nullptr;
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switch (*Action.Special) {
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case SPC_Reciprocal:
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// Simplify reciprocal.
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return BinaryOperator::Create(
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Instruction::FDiv, ConstantFP::get(II->getArgOperand(0)->getType(), 1),
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II->getArgOperand(0), II->getName());
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}
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}
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Instruction *InstCombiner::visitVAStartInst(VAStartInst &I) {
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Instruction *InstCombiner::visitVAStartInst(VAStartInst &I) {
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removeTriviallyEmptyRange(I, Intrinsic::vastart, Intrinsic::vaend, *this);
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removeTriviallyEmptyRange(I, Intrinsic::vastart, Intrinsic::vaend, *this);
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return nullptr;
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return nullptr;
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@ -1587,6 +1834,9 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
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if (Changed) return II;
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if (Changed) return II;
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}
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}
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if (Instruction *I = SimplifyNVVMIntrinsic(II, *this))
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return I;
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auto SimplifyDemandedVectorEltsLow = [this](Value *Op, unsigned Width,
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auto SimplifyDemandedVectorEltsLow = [this](Value *Op, unsigned Width,
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unsigned DemandedWidth) {
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unsigned DemandedWidth) {
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APInt UndefElts(Width, 0);
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APInt UndefElts(Width, 0);
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@ -0,0 +1,471 @@
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; Check that nvvm intrinsics get simplified to target-generic intrinsics where
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; possible.
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;
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; We run this test twice; once with ftz on, and again with ftz off. Behold the
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; hackery:
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; RUN: cat %s > %t.ftz
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; RUN: echo 'attributes #0 = { "nvptx-f32ftz" = "true" }' >> %t.ftz
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; RUN: opt < %t.ftz -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=FTZ
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; RUN: cat %s > %t.noftz
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; RUN: echo 'attributes #0 = { "nvptx-f32ftz" = "false" }' >> %t.noftz
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; RUN: opt < %t.noftz -instcombine -S | FileCheck %s --check-prefix=CHECK --check-prefix=NOFTZ
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; We handle nvvm intrinsics with ftz variants as follows:
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; - If the module is in ftz mode, the ftz variant is transformed into the
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; regular llvm intrinsic, and the non-ftz variant is left alone.
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; - If the module is not in ftz mode, it's the reverse: Only the non-ftz
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; variant is transformed, and the ftz variant is left alone.
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; Check NVVM intrinsics that map directly to LLVM target-generic intrinsics.
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; CHECK-LABEL: @ceil_double
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define double @ceil_double(double %a) #0 {
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; CHECK: call double @llvm.ceil.f64
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%ret = call double @llvm.nvvm.ceil.d(double %a)
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ret double %ret
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}
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; CHECK-LABEL: @ceil_float
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define float @ceil_float(float %a) #0 {
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; NOFTZ: call float @llvm.ceil.f32
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; FTZ: call float @llvm.nvvm.ceil.f
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%ret = call float @llvm.nvvm.ceil.f(float %a)
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ret float %ret
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}
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; CHECK-LABEL: @ceil_float_ftz
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define float @ceil_float_ftz(float %a) #0 {
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; NOFTZ: call float @llvm.nvvm.ceil.ftz.f
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; FTZ: call float @llvm.ceil.f32
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%ret = call float @llvm.nvvm.ceil.ftz.f(float %a)
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ret float %ret
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}
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; CHECK-LABEL: @fabs_double
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define double @fabs_double(double %a) #0 {
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; CHECK: call double @llvm.fabs.f64
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%ret = call double @llvm.nvvm.fabs.d(double %a)
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ret double %ret
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}
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; CHECK-LABEL: @fabs_float
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define float @fabs_float(float %a) #0 {
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; NOFTZ: call float @llvm.fabs.f32
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; FTZ: call float @llvm.nvvm.fabs.f
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||||||
|
%ret = call float @llvm.nvvm.fabs.f(float %a)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @fabs_float_ftz
|
||||||
|
define float @fabs_float_ftz(float %a) #0 {
|
||||||
|
; NOFTZ: call float @llvm.nvvm.fabs.ftz.f
|
||||||
|
; FTZ: call float @llvm.fabs.f32
|
||||||
|
%ret = call float @llvm.nvvm.fabs.ftz.f(float %a)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
|
||||||
|
; CHECK-LABEL: @floor_double
|
||||||
|
define double @floor_double(double %a) #0 {
|
||||||
|
; CHECK: call double @llvm.floor.f64
|
||||||
|
%ret = call double @llvm.nvvm.floor.d(double %a)
|
||||||
|
ret double %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @floor_float
|
||||||
|
define float @floor_float(float %a) #0 {
|
||||||
|
; NOFTZ: call float @llvm.floor.f32
|
||||||
|
; FTZ: call float @llvm.nvvm.floor.f
|
||||||
|
%ret = call float @llvm.nvvm.floor.f(float %a)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @floor_float_ftz
|
||||||
|
define float @floor_float_ftz(float %a) #0 {
|
||||||
|
; NOFTZ: call float @llvm.nvvm.floor.ftz.f
|
||||||
|
; FTZ: call float @llvm.floor.f32
|
||||||
|
%ret = call float @llvm.nvvm.floor.ftz.f(float %a)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
|
||||||
|
; CHECK-LABEL: @fma_double
|
||||||
|
define double @fma_double(double %a, double %b, double %c) #0 {
|
||||||
|
; CHECK: call double @llvm.fma.f64
|
||||||
|
%ret = call double @llvm.nvvm.fma.rn.d(double %a, double %b, double %c)
|
||||||
|
ret double %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @fma_float
|
||||||
|
define float @fma_float(float %a, float %b, float %c) #0 {
|
||||||
|
; NOFTZ: call float @llvm.fma.f32
|
||||||
|
; FTZ: call float @llvm.nvvm.fma.rn.f
|
||||||
|
%ret = call float @llvm.nvvm.fma.rn.f(float %a, float %b, float %c)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @fma_float_ftz
|
||||||
|
define float @fma_float_ftz(float %a, float %b, float %c) #0 {
|
||||||
|
; NOFTZ: call float @llvm.nvvm.fma.rn.ftz.f
|
||||||
|
; FTZ: call float @llvm.fma.f32
|
||||||
|
%ret = call float @llvm.nvvm.fma.rn.ftz.f(float %a, float %b, float %c)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
|
||||||
|
; CHECK-LABEL: @fmax_double
|
||||||
|
define double @fmax_double(double %a, double %b) #0 {
|
||||||
|
; CHECK: call double @llvm.maxnum.f64
|
||||||
|
%ret = call double @llvm.nvvm.fmax.d(double %a, double %b)
|
||||||
|
ret double %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @fmax_float
|
||||||
|
define float @fmax_float(float %a, float %b) #0 {
|
||||||
|
; NOFTZ: call float @llvm.maxnum.f32
|
||||||
|
; FTZ: call float @llvm.nvvm.fmax.f
|
||||||
|
%ret = call float @llvm.nvvm.fmax.f(float %a, float %b)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @fmax_float_ftz
|
||||||
|
define float @fmax_float_ftz(float %a, float %b) #0 {
|
||||||
|
; NOFTZ: call float @llvm.nvvm.fmax.ftz.f
|
||||||
|
; FTZ: call float @llvm.maxnum.f32
|
||||||
|
%ret = call float @llvm.nvvm.fmax.ftz.f(float %a, float %b)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
|
||||||
|
; CHECK-LABEL: @fmin_double
|
||||||
|
define double @fmin_double(double %a, double %b) #0 {
|
||||||
|
; CHECK: call double @llvm.minnum.f64
|
||||||
|
%ret = call double @llvm.nvvm.fmin.d(double %a, double %b)
|
||||||
|
ret double %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @fmin_float
|
||||||
|
define float @fmin_float(float %a, float %b) #0 {
|
||||||
|
; NOFTZ: call float @llvm.minnum.f32
|
||||||
|
; FTZ: call float @llvm.nvvm.fmin.f
|
||||||
|
%ret = call float @llvm.nvvm.fmin.f(float %a, float %b)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @fmin_float_ftz
|
||||||
|
define float @fmin_float_ftz(float %a, float %b) #0 {
|
||||||
|
; NOFTZ: call float @llvm.nvvm.fmin.ftz.f
|
||||||
|
; FTZ: call float @llvm.minnum.f32
|
||||||
|
%ret = call float @llvm.nvvm.fmin.ftz.f(float %a, float %b)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
|
||||||
|
; CHECK-LABEL: @round_double
|
||||||
|
define double @round_double(double %a) #0 {
|
||||||
|
; CHECK: call double @llvm.round.f64
|
||||||
|
%ret = call double @llvm.nvvm.round.d(double %a)
|
||||||
|
ret double %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @round_float
|
||||||
|
define float @round_float(float %a) #0 {
|
||||||
|
; NOFTZ: call float @llvm.round.f32
|
||||||
|
; FTZ: call float @llvm.nvvm.round.f
|
||||||
|
%ret = call float @llvm.nvvm.round.f(float %a)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @round_float_ftz
|
||||||
|
define float @round_float_ftz(float %a) #0 {
|
||||||
|
; NOFTZ: call float @llvm.nvvm.round.ftz.f
|
||||||
|
; FTZ: call float @llvm.round.f32
|
||||||
|
%ret = call float @llvm.nvvm.round.ftz.f(float %a)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
|
||||||
|
; CHECK-LABEL: @trunc_double
|
||||||
|
define double @trunc_double(double %a) #0 {
|
||||||
|
; CHECK: call double @llvm.trunc.f64
|
||||||
|
%ret = call double @llvm.nvvm.trunc.d(double %a)
|
||||||
|
ret double %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @trunc_float
|
||||||
|
define float @trunc_float(float %a) #0 {
|
||||||
|
; NOFTZ: call float @llvm.trunc.f32
|
||||||
|
; FTZ: call float @llvm.nvvm.trunc.f
|
||||||
|
%ret = call float @llvm.nvvm.trunc.f(float %a)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @trunc_float_ftz
|
||||||
|
define float @trunc_float_ftz(float %a) #0 {
|
||||||
|
; NOFTZ: call float @llvm.nvvm.trunc.ftz.f
|
||||||
|
; FTZ: call float @llvm.trunc.f32
|
||||||
|
%ret = call float @llvm.nvvm.trunc.ftz.f(float %a)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
|
||||||
|
; Check NVVM intrinsics that correspond to LLVM cast operations.
|
||||||
|
|
||||||
|
; CHECK-LABEL: @test_d2i
|
||||||
|
define i32 @test_d2i(double %a) #0 {
|
||||||
|
; CHECK: fptosi double %a to i32
|
||||||
|
%ret = call i32 @llvm.nvvm.d2i.rz(double %a)
|
||||||
|
ret i32 %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @test_f2i
|
||||||
|
define i32 @test_f2i(float %a) #0 {
|
||||||
|
; CHECK: fptosi float %a to i32
|
||||||
|
%ret = call i32 @llvm.nvvm.f2i.rz(float %a)
|
||||||
|
ret i32 %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @test_d2ll
|
||||||
|
define i64 @test_d2ll(double %a) #0 {
|
||||||
|
; CHECK: fptosi double %a to i64
|
||||||
|
%ret = call i64 @llvm.nvvm.d2ll.rz(double %a)
|
||||||
|
ret i64 %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @test_f2ll
|
||||||
|
define i64 @test_f2ll(float %a) #0 {
|
||||||
|
; CHECK: fptosi float %a to i64
|
||||||
|
%ret = call i64 @llvm.nvvm.f2ll.rz(float %a)
|
||||||
|
ret i64 %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @test_d2ui
|
||||||
|
define i32 @test_d2ui(double %a) #0 {
|
||||||
|
; CHECK: fptoui double %a to i32
|
||||||
|
%ret = call i32 @llvm.nvvm.d2ui.rz(double %a)
|
||||||
|
ret i32 %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @test_f2ui
|
||||||
|
define i32 @test_f2ui(float %a) #0 {
|
||||||
|
; CHECK: fptoui float %a to i32
|
||||||
|
%ret = call i32 @llvm.nvvm.f2ui.rz(float %a)
|
||||||
|
ret i32 %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @test_d2ull
|
||||||
|
define i64 @test_d2ull(double %a) #0 {
|
||||||
|
; CHECK: fptoui double %a to i64
|
||||||
|
%ret = call i64 @llvm.nvvm.d2ull.rz(double %a)
|
||||||
|
ret i64 %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @test_f2ull
|
||||||
|
define i64 @test_f2ull(float %a) #0 {
|
||||||
|
; CHECK: fptoui float %a to i64
|
||||||
|
%ret = call i64 @llvm.nvvm.f2ull.rz(float %a)
|
||||||
|
ret i64 %ret
|
||||||
|
}
|
||||||
|
|
||||||
|
; CHECK-LABEL: @test_i2d
|
||||||
|
define double @test_i2d(i32 %a) #0 {
|
||||||
|
; CHECK: sitofp i32 %a to double
|
||||||
|
%ret = call double @llvm.nvvm.i2d.rz(i32 %a)
|
||||||
|
ret double %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @test_i2f
|
||||||
|
define float @test_i2f(i32 %a) #0 {
|
||||||
|
; CHECK: sitofp i32 %a to float
|
||||||
|
%ret = call float @llvm.nvvm.i2f.rz(i32 %a)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @test_ll2d
|
||||||
|
define double @test_ll2d(i64 %a) #0 {
|
||||||
|
; CHECK: sitofp i64 %a to double
|
||||||
|
%ret = call double @llvm.nvvm.ll2d.rz(i64 %a)
|
||||||
|
ret double %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @test_ll2f
|
||||||
|
define float @test_ll2f(i64 %a) #0 {
|
||||||
|
; CHECK: sitofp i64 %a to float
|
||||||
|
%ret = call float @llvm.nvvm.ll2f.rz(i64 %a)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @test_ui2d
|
||||||
|
define double @test_ui2d(i32 %a) #0 {
|
||||||
|
; CHECK: uitofp i32 %a to double
|
||||||
|
%ret = call double @llvm.nvvm.ui2d.rz(i32 %a)
|
||||||
|
ret double %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @test_ui2f
|
||||||
|
define float @test_ui2f(i32 %a) #0 {
|
||||||
|
; CHECK: uitofp i32 %a to float
|
||||||
|
%ret = call float @llvm.nvvm.ui2f.rz(i32 %a)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @test_ull2d
|
||||||
|
define double @test_ull2d(i64 %a) #0 {
|
||||||
|
; CHECK: uitofp i64 %a to double
|
||||||
|
%ret = call double @llvm.nvvm.ull2d.rz(i64 %a)
|
||||||
|
ret double %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @test_ull2f
|
||||||
|
define float @test_ull2f(i64 %a) #0 {
|
||||||
|
; CHECK: uitofp i64 %a to float
|
||||||
|
%ret = call float @llvm.nvvm.ull2f.rz(i64 %a)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
|
||||||
|
; Check NVVM intrinsics that map to LLVM binary operations.
|
||||||
|
|
||||||
|
; CHECK-LABEL: @test_add_rn_d
|
||||||
|
define double @test_add_rn_d(double %a, double %b) #0 {
|
||||||
|
; CHECK: fadd
|
||||||
|
%ret = call double @llvm.nvvm.add.rn.d(double %a, double %b)
|
||||||
|
ret double %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @test_add_rn_f
|
||||||
|
define float @test_add_rn_f(float %a, float %b) #0 {
|
||||||
|
; NOFTZ: fadd
|
||||||
|
; FTZ: call float @llvm.nvvm.add.rn.f
|
||||||
|
%ret = call float @llvm.nvvm.add.rn.f(float %a, float %b)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @test_add_rn_f_ftz
|
||||||
|
define float @test_add_rn_f_ftz(float %a, float %b) #0 {
|
||||||
|
; NOFTZ: call float @llvm.nvvm.add.rn.f
|
||||||
|
; FTZ: fadd
|
||||||
|
%ret = call float @llvm.nvvm.add.rn.ftz.f(float %a, float %b)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
|
||||||
|
; CHECK-LABEL: @test_mul_rn_d
|
||||||
|
define double @test_mul_rn_d(double %a, double %b) #0 {
|
||||||
|
; CHECK: fmul
|
||||||
|
%ret = call double @llvm.nvvm.mul.rn.d(double %a, double %b)
|
||||||
|
ret double %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @test_mul_rn_f
|
||||||
|
define float @test_mul_rn_f(float %a, float %b) #0 {
|
||||||
|
; NOFTZ: fmul
|
||||||
|
; FTZ: call float @llvm.nvvm.mul.rn.f
|
||||||
|
%ret = call float @llvm.nvvm.mul.rn.f(float %a, float %b)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @test_mul_rn_f_ftz
|
||||||
|
define float @test_mul_rn_f_ftz(float %a, float %b) #0 {
|
||||||
|
; NOFTZ: call float @llvm.nvvm.mul.rn.f
|
||||||
|
; FTZ: fmul
|
||||||
|
%ret = call float @llvm.nvvm.mul.rn.ftz.f(float %a, float %b)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
|
||||||
|
; CHECK-LABEL: @test_div_rn_d
|
||||||
|
define double @test_div_rn_d(double %a, double %b) #0 {
|
||||||
|
; CHECK: fdiv
|
||||||
|
%ret = call double @llvm.nvvm.div.rn.d(double %a, double %b)
|
||||||
|
ret double %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @test_div_rn_f
|
||||||
|
define float @test_div_rn_f(float %a, float %b) #0 {
|
||||||
|
; NOFTZ: fdiv
|
||||||
|
; FTZ: call float @llvm.nvvm.div.rn.f
|
||||||
|
%ret = call float @llvm.nvvm.div.rn.f(float %a, float %b)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @test_div_rn_f_ftz
|
||||||
|
define float @test_div_rn_f_ftz(float %a, float %b) #0 {
|
||||||
|
; NOFTZ: call float @llvm.nvvm.div.rn.f
|
||||||
|
; FTZ: fdiv
|
||||||
|
%ret = call float @llvm.nvvm.div.rn.ftz.f(float %a, float %b)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
|
||||||
|
; Check NVVM intrinsics that require us to emit custom IR.
|
||||||
|
|
||||||
|
; CHECK-LABEL: @test_rcp_rn_f
|
||||||
|
define float @test_rcp_rn_f(float %a) #0 {
|
||||||
|
; NOFTZ: fdiv float 1.0{{.*}} %a
|
||||||
|
; FTZ: call float @llvm.nvvm.rcp.rn.f
|
||||||
|
%ret = call float @llvm.nvvm.rcp.rn.f(float %a)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @test_rcp_rn_f_ftz
|
||||||
|
define float @test_rcp_rn_f_ftz(float %a) #0 {
|
||||||
|
; NOFTZ: call float @llvm.nvvm.rcp.rn.f
|
||||||
|
; FTZ: fdiv float 1.0{{.*}} %a
|
||||||
|
%ret = call float @llvm.nvvm.rcp.rn.ftz.f(float %a)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
|
||||||
|
; CHECK-LABEL: @test_sqrt_rn_d
|
||||||
|
define double @test_sqrt_rn_d(double %a) #0 {
|
||||||
|
; CHECK: call double @llvm.sqrt.f64(double %a)
|
||||||
|
%ret = call double @llvm.nvvm.sqrt.rn.d(double %a)
|
||||||
|
ret double %ret
|
||||||
|
}
|
||||||
|
; nvvm.sqrt.f is a special case: It goes to a llvm.sqrt.f
|
||||||
|
; CHECK-LABEL: @test_sqrt_f
|
||||||
|
define float @test_sqrt_f(float %a) #0 {
|
||||||
|
; CHECK: call float @llvm.sqrt.f32(float %a)
|
||||||
|
%ret = call float @llvm.nvvm.sqrt.f(float %a)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @test_sqrt_rn_f
|
||||||
|
define float @test_sqrt_rn_f(float %a) #0 {
|
||||||
|
; NOFTZ: call float @llvm.sqrt.f32(float %a)
|
||||||
|
; FTZ: call float @llvm.nvvm.sqrt.rn.f
|
||||||
|
%ret = call float @llvm.nvvm.sqrt.rn.f(float %a)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
; CHECK-LABEL: @test_sqrt_rn_f_ftz
|
||||||
|
define float @test_sqrt_rn_f_ftz(float %a) #0 {
|
||||||
|
; NOFTZ: call float @llvm.nvvm.sqrt.rn.f
|
||||||
|
; FTZ: call float @llvm.sqrt.f32(float %a)
|
||||||
|
%ret = call float @llvm.nvvm.sqrt.rn.ftz.f(float %a)
|
||||||
|
ret float %ret
|
||||||
|
}
|
||||||
|
|
||||||
|
declare double @llvm.nvvm.add.rn.d(double, double)
|
||||||
|
declare float @llvm.nvvm.add.rn.f(float, float)
|
||||||
|
declare float @llvm.nvvm.add.rn.ftz.f(float, float)
|
||||||
|
declare double @llvm.nvvm.ceil.d(double)
|
||||||
|
declare float @llvm.nvvm.ceil.f(float)
|
||||||
|
declare float @llvm.nvvm.ceil.ftz.f(float)
|
||||||
|
declare float @llvm.nvvm.d2f.rm(double)
|
||||||
|
declare float @llvm.nvvm.d2f.rm.ftz(double)
|
||||||
|
declare float @llvm.nvvm.d2f.rp(double)
|
||||||
|
declare float @llvm.nvvm.d2f.rp.ftz(double)
|
||||||
|
declare float @llvm.nvvm.d2f.rz(double)
|
||||||
|
declare float @llvm.nvvm.d2f.rz.ftz(double)
|
||||||
|
declare i32 @llvm.nvvm.d2i.rz(double)
|
||||||
|
declare i64 @llvm.nvvm.d2ll.rz(double)
|
||||||
|
declare i32 @llvm.nvvm.d2ui.rz(double)
|
||||||
|
declare i64 @llvm.nvvm.d2ull.rz(double)
|
||||||
|
declare double @llvm.nvvm.div.rn.d(double, double)
|
||||||
|
declare float @llvm.nvvm.div.rn.f(float, float)
|
||||||
|
declare float @llvm.nvvm.div.rn.ftz.f(float, float)
|
||||||
|
declare i16 @llvm.nvvm.f2h.rz(float)
|
||||||
|
declare i16 @llvm.nvvm.f2h.rz.ftz(float)
|
||||||
|
declare i32 @llvm.nvvm.f2i.rz(float)
|
||||||
|
declare i32 @llvm.nvvm.f2i.rz.ftz(float)
|
||||||
|
declare i64 @llvm.nvvm.f2ll.rz(float)
|
||||||
|
declare i64 @llvm.nvvm.f2ll.rz.ftz(float)
|
||||||
|
declare i32 @llvm.nvvm.f2ui.rz(float)
|
||||||
|
declare i32 @llvm.nvvm.f2ui.rz.ftz(float)
|
||||||
|
declare i64 @llvm.nvvm.f2ull.rz(float)
|
||||||
|
declare i64 @llvm.nvvm.f2ull.rz.ftz(float)
|
||||||
|
declare double @llvm.nvvm.fabs.d(double)
|
||||||
|
declare float @llvm.nvvm.fabs.f(float)
|
||||||
|
declare float @llvm.nvvm.fabs.ftz.f(float)
|
||||||
|
declare double @llvm.nvvm.floor.d(double)
|
||||||
|
declare float @llvm.nvvm.floor.f(float)
|
||||||
|
declare float @llvm.nvvm.floor.ftz.f(float)
|
||||||
|
declare double @llvm.nvvm.fma.rn.d(double, double, double)
|
||||||
|
declare float @llvm.nvvm.fma.rn.f(float, float, float)
|
||||||
|
declare float @llvm.nvvm.fma.rn.ftz.f(float, float, float)
|
||||||
|
declare double @llvm.nvvm.fmax.d(double, double)
|
||||||
|
declare float @llvm.nvvm.fmax.f(float, float)
|
||||||
|
declare float @llvm.nvvm.fmax.ftz.f(float, float)
|
||||||
|
declare double @llvm.nvvm.fmin.d(double, double)
|
||||||
|
declare float @llvm.nvvm.fmin.f(float, float)
|
||||||
|
declare float @llvm.nvvm.fmin.ftz.f(float, float)
|
||||||
|
declare double @llvm.nvvm.i2d.rz(i32)
|
||||||
|
declare float @llvm.nvvm.i2f.rz(i32)
|
||||||
|
declare double @llvm.nvvm.ll2d.rz(i64)
|
||||||
|
declare float @llvm.nvvm.ll2f.rz(i64)
|
||||||
|
declare double @llvm.nvvm.lohi.i2d(i32, i32)
|
||||||
|
declare double @llvm.nvvm.mul.rn.d(double, double)
|
||||||
|
declare float @llvm.nvvm.mul.rn.f(float, float)
|
||||||
|
declare float @llvm.nvvm.mul.rn.ftz.f(float, float)
|
||||||
|
declare double @llvm.nvvm.rcp.rm.d(double)
|
||||||
|
declare double @llvm.nvvm.rcp.rn.d(double)
|
||||||
|
declare float @llvm.nvvm.rcp.rn.f(float)
|
||||||
|
declare float @llvm.nvvm.rcp.rn.ftz.f(float)
|
||||||
|
declare double @llvm.nvvm.round.d(double)
|
||||||
|
declare float @llvm.nvvm.round.f(float)
|
||||||
|
declare float @llvm.nvvm.round.ftz.f(float)
|
||||||
|
declare float @llvm.nvvm.sqrt.f(float)
|
||||||
|
declare double @llvm.nvvm.sqrt.rn.d(double)
|
||||||
|
declare float @llvm.nvvm.sqrt.rn.f(float)
|
||||||
|
declare float @llvm.nvvm.sqrt.rn.ftz.f(float)
|
||||||
|
declare double @llvm.nvvm.trunc.d(double)
|
||||||
|
declare float @llvm.nvvm.trunc.f(float)
|
||||||
|
declare float @llvm.nvvm.trunc.ftz.f(float)
|
||||||
|
declare double @llvm.nvvm.ui2d.rz(i32)
|
||||||
|
declare float @llvm.nvvm.ui2f.rn(i32)
|
||||||
|
declare float @llvm.nvvm.ui2f.rz(i32)
|
||||||
|
declare double @llvm.nvvm.ull2d.rz(i64)
|
||||||
|
declare float @llvm.nvvm.ull2f.rz(i64)
|
||||||
Loading…
Reference in New Issue