forked from OSchip/llvm-project
R600/SI: Enable named operand table for SALU instructions
llvm-svn: 218358
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parent
0b682d42de
commit
69612d6027
llvm/lib/Target/R600
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@ -164,6 +164,8 @@ class SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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let mayStore = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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let hasSideEffects = 0;
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let SALU = 1;
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let SALU = 1;
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let UseNamedOperandTable = 1;
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}
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}
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class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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@ -174,6 +176,8 @@ class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
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let mayStore = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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let hasSideEffects = 0;
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let SALU = 1;
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let SALU = 1;
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let UseNamedOperandTable = 1;
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}
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}
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class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
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class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
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@ -183,6 +187,8 @@ class SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> :
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let mayStore = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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let hasSideEffects = 0;
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let SALU = 1;
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let SALU = 1;
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let UseNamedOperandTable = 1;
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}
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}
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class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> :
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class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> :
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@ -192,6 +198,8 @@ class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> :
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let mayStore = 0;
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let mayStore = 0;
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let hasSideEffects = 0;
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let hasSideEffects = 0;
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let SALU = 1;
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let SALU = 1;
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let UseNamedOperandTable = 1;
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}
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}
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class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm,
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class SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm,
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