maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[AMDGPU] Sign extend AShr when promoting (instead of zero extending) 

llvm-svn: 283130
This commit is contained in:
Konstantin Zhuravlyov 2016-10-03 18:29:01 +00:00
parent b4d2678c6f
commit 691e2e020b
2 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
View File

@ -172,8 +172,8 @@ bool AMDGPUCodeGenPrepare::isI32Ty(const Type *T) const {
}
bool AMDGPUCodeGenPrepare::isSigned(const BinaryOperator &I) const {
return I.getOpcode() == Instruction::SDiv ||
I.getOpcode() == Instruction::SRem;
return I.getOpcode() == Instruction::AShr ||
I.getOpcode() == Instruction::SDiv || I.getOpcode() == Instruction::SRem;
}
bool AMDGPUCodeGenPrepare::isSigned(const SelectInst &I) const {

16
llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-i16-to-i32.ll
View File

@ -226,8 +226,8 @@ define i16 @lshr_exact_i16(i16 %a, i16 %b) {
}
; VI-LABEL: @ashr_i16(
; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
; VI: %[[A_32:[0-9]+]] = sext i16 %a to i32
; VI: %[[B_32:[0-9]+]] = sext i16 %b to i32
; VI: %[[R_32:[0-9]+]] = ashr i32 %[[A_32]], %[[B_32]]
; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
; VI: ret i16 %[[R_16]]
@ -237,8 +237,8 @@ define i16 @ashr_i16(i16 %a, i16 %b) {
}
; VI-LABEL: @ashr_exact_i16(
; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32
; VI: %[[B_32:[0-9]+]] = zext i16 %b to i32
; VI: %[[A_32:[0-9]+]] = sext i16 %a to i32
; VI: %[[B_32:[0-9]+]] = sext i16 %b to i32
; VI: %[[R_32:[0-9]+]] = ashr exact i32 %[[A_32]], %[[B_32]]
; VI: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16
; VI: ret i16 %[[R_16]]
@ -651,8 +651,8 @@ define <3 x i16> @lshr_exact_3xi16(<3 x i16> %a, <3 x i16> %b) {
}
; VI-LABEL: @ashr_3xi16(
; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
; VI: %[[A_32:[0-9]+]] = sext <3 x i16> %a to <3 x i32>
; VI: %[[B_32:[0-9]+]] = sext <3 x i16> %b to <3 x i32>
; VI: %[[R_32:[0-9]+]] = ashr <3 x i32> %[[A_32]], %[[B_32]]
; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
; VI: ret <3 x i16> %[[R_16]]
@ -662,8 +662,8 @@ define <3 x i16> @ashr_3xi16(<3 x i16> %a, <3 x i16> %b) {
}
; VI-LABEL: @ashr_exact_3xi16(
; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32>
; VI: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32>
; VI: %[[A_32:[0-9]+]] = sext <3 x i16> %a to <3 x i32>
; VI: %[[B_32:[0-9]+]] = sext <3 x i16> %b to <3 x i32>
; VI: %[[R_32:[0-9]+]] = ashr exact <3 x i32> %[[A_32]], %[[B_32]]
; VI: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16>
; VI: ret <3 x i16> %[[R_16]]