forked from OSchip/llvm-project
[RISCV] Don't use DCI.CombineTo to replace a single result. NFCI
Just return the new node, which is the standard practice. I also noticed what appeared to be an unnecessary attempt at creating an ANY_EXTEND where the type should already be correct. I replace with an assert to verify the type. Differential Revision: https://reviews.llvm.org/D90444
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@ -1086,9 +1086,9 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
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// conversion is unnecessary and can be replaced with an ANY_EXTEND
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// of the FMV_W_X_RV64 operand.
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if (Op0->getOpcode() == RISCVISD::FMV_W_X_RV64) {
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SDValue AExtOp =
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DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0.getOperand(0));
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return DCI.CombineTo(N, AExtOp);
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assert(Op0.getOperand(0).getValueType() == MVT::i64 &&
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"Unexpected value type!");
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return Op0.getOperand(0);
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}
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// This is a target-specific version of a DAGCombine performed in
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@ -1101,15 +1101,13 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
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SDValue NewFMV = DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64,
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Op0.getOperand(0));
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APInt SignBit = APInt::getSignMask(32).sext(64);
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if (Op0.getOpcode() == ISD::FNEG) {
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return DCI.CombineTo(N,
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DAG.getNode(ISD::XOR, DL, MVT::i64, NewFMV,
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DAG.getConstant(SignBit, DL, MVT::i64)));
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}
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if (Op0.getOpcode() == ISD::FNEG)
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return DAG.getNode(ISD::XOR, DL, MVT::i64, NewFMV,
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DAG.getConstant(SignBit, DL, MVT::i64));
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assert(Op0.getOpcode() == ISD::FABS);
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return DCI.CombineTo(N,
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DAG.getNode(ISD::AND, DL, MVT::i64, NewFMV,
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DAG.getConstant(~SignBit, DL, MVT::i64)));
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return DAG.getNode(ISD::AND, DL, MVT::i64, NewFMV,
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DAG.getConstant(~SignBit, DL, MVT::i64));
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}
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}
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