maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

AMDGPU: Fix visiting physreg dest users when folding immediate copies 

This can fold the immediate into the physical destination, but this
should not look for further users of the register. Fixes regression
introduced by 766cb615a3.
This commit is contained in:
Matt Arsenault 2020-08-08 20:28:48 -04:00
parent a3036b3863
commit 68fab44acf
3 changed files with 70 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
View File

@ -666,6 +666,7 @@ void SIFoldOperands::foldOperand(
return;
const TargetRegisterClass *DestRC = TRI->getRegClassForReg(*MRI, DestReg);
if (!DestReg.isPhysical()) {
if (TRI->isSGPRClass(SrcRC) && TRI->hasVectorRegisters(DestRC)) {
MachineRegisterInfo::use_iterator NextUse;
SmallVector<FoldCandidate, 4> CopyUses;
@ -693,6 +694,7 @@ void SIFoldOperands::foldOperand(
CopiesToReplace.push_back(UseMI);
return;
}
}
// In order to fold immediates into copies, we need to change the
// copy to a MOV.

23
llvm/test/CodeGen/AMDGPU/fold-imm-copy.mir
View File

@ -87,3 +87,26 @@ body: |
S_ENDPGM 0, implicit $vgpr0
...
# The users of $vgpr1 should not be visited for further immediate
# folding.
# GCN-LABEL: name: no_fold_physreg_users_vgpr{{$}}
# GCN: $vgpr1 = V_MOV_B32_e32 0, implicit $exec
# GCN-NEXT: S_NOP 0, implicit-def $vgpr1
# GCN-NEXT: %2:vgpr_32 = COPY $vgpr1
# GCN-NEXT: $vgpr2 = COPY %2
---
name: no_fold_physreg_users_vgpr
tracksRegLiveness: true
body: |
bb.0:
%0:sreg_32 = S_MOV_B32 0
%1:vgpr_32 = COPY %0
$vgpr1 = COPY %0
S_NOP 0, implicit-def $vgpr1
%2:vgpr_32 = COPY $vgpr1
$vgpr2 = COPY %2
S_ENDPGM 0
...

22
llvm/test/CodeGen/AMDGPU/visit-physreg-vgpr-imm-folding-bug.ll Normal file
View File

@ -0,0 +1,22 @@
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s
; Make sure the return value of the first call is not overwritten with
; a constant before the fadd use.
; CHECK-LABEL: vgpr_multi_use_imm_fold:
; CHECK: v_mov_b32_e32 v0, 0{{$}}
; CHECK: v_mov_b32_e32 v1, 2.0{{$}}
; CHECK: s_swappc_b64
; CHECK-NEXT: v_add_f64 v[0:1], v[0:1], 0
; CHECK: s_swappc_b64
define amdgpu_kernel void @vgpr_multi_use_imm_fold() {
entry:
store double 0.0, double addrspace(1)* undef, align 8
%call0 = tail call fastcc double @__ocml_log_f64(double 2.0)
%op = fadd double %call0, 0.0
%call1 = tail call fastcc double @__ocml_sqrt_f64(double %op)
ret void
}
declare hidden fastcc double @__ocml_log_f64(double)
declare hidden fastcc double @__ocml_sqrt_f64(double)