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AMDGPU/GlobalISel: Switch test to checking final ISA 

The naming convention is for unprefixed .ll tests to check the final
ISA instructions.
This commit is contained in:
Matt Arsenault 2020-04-01 13:00:55 -04:00 committed by Matt Arsenault
parent 5e4e8d0388
commit 68e283940a
1 changed files with 206 additions and 333 deletions
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539
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.ltolz.ll
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@ -1,404 +1,277 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -stop-after=legalizer -o - %s | FileCheck -check-prefix=GCN %s ; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -o - %s | FileCheck -check-prefix=GCN %s
define amdgpu_ps <4 x float> @sample_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %lod) { define amdgpu_ps <4 x float> @sample_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %lod) {
; GCN-LABEL: name: sample_l_1d ; GCN-LABEL: sample_l_1d:
; GCN: bb.1.main_body: ; GCN: ; %bb.0: ; %main_body
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0 ; GCN-NEXT: s_mov_b32 s0, s2
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 ; GCN-NEXT: s_mov_b32 s1, s3
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 ; GCN-NEXT: s_mov_b32 s2, s4
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 ; GCN-NEXT: s_mov_b32 s3, s5
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 ; GCN-NEXT: s_mov_b32 s4, s6
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 ; GCN-NEXT: s_mov_b32 s5, s7
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 ; GCN-NEXT: s_mov_b32 s6, s8
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 ; GCN-NEXT: s_mov_b32 s7, s9
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 ; GCN-NEXT: s_mov_b32 s8, s10
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10 ; GCN-NEXT: s_mov_b32 s9, s11
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11 ; GCN-NEXT: s_mov_b32 s10, s12
; GCN: [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12 ; GCN-NEXT: s_mov_b32 s11, s13
; GCN: [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13 ; GCN-NEXT: image_sample_lz v[0:3], v0, s[0:7], s[8:11] dmask:0xf
; GCN: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32) ; GCN-NEXT: ; return to shader part epilog
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.lz.1d), 15, [[COPY12]](s32), [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GCN: $vgpr0 = COPY [[UV]](s32)
; GCN: $vgpr1 = COPY [[UV1]](s32)
; GCN: $vgpr2 = COPY [[UV2]](s32)
; GCN: $vgpr3 = COPY [[UV3]](s32)
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.l.1d.v4f32.f32(i32 15, float %s, float 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.sample.l.1d.v4f32.f32(i32 15, float %s, float 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
define amdgpu_ps <4 x float> @sample_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %lod) { define amdgpu_ps <4 x float> @sample_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %lod) {
; GCN-LABEL: name: sample_l_2d ; GCN-LABEL: sample_l_2d:
; GCN: bb.1.main_body: ; GCN: ; %bb.0: ; %main_body
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1 ; GCN-NEXT: s_mov_b32 s0, s2
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 ; GCN-NEXT: s_mov_b32 s1, s3
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 ; GCN-NEXT: s_mov_b32 s2, s4
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 ; GCN-NEXT: s_mov_b32 s3, s5
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 ; GCN-NEXT: s_mov_b32 s4, s6
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 ; GCN-NEXT: s_mov_b32 s5, s7
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 ; GCN-NEXT: s_mov_b32 s6, s8
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 ; GCN-NEXT: s_mov_b32 s7, s9
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 ; GCN-NEXT: s_mov_b32 s8, s10
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10 ; GCN-NEXT: s_mov_b32 s9, s11
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11 ; GCN-NEXT: s_mov_b32 s10, s12
; GCN: [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12 ; GCN-NEXT: s_mov_b32 s11, s13
; GCN: [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13 ; GCN-NEXT: image_sample_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf
; GCN: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GCN-NEXT: ; return to shader part epilog
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GCN: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32)
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.lz.2d), 15, [[BUILD_VECTOR2]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GCN: $vgpr0 = COPY [[UV]](s32)
; GCN: $vgpr1 = COPY [[UV1]](s32)
; GCN: $vgpr2 = COPY [[UV2]](s32)
; GCN: $vgpr3 = COPY [[UV3]](s32)
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.l.2d.v4f32.f32(i32 15, float %s, float %t, float -0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.sample.l.2d.v4f32.f32(i32 15, float %s, float %t, float -0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
define amdgpu_ps <4 x float> @sample_c_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %lod) { define amdgpu_ps <4 x float> @sample_c_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %lod) {
; GCN-LABEL: name: sample_c_l_1d ; GCN-LABEL: sample_c_l_1d:
; GCN: bb.1.main_body: ; GCN: ; %bb.0: ; %main_body
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1 ; GCN-NEXT: s_mov_b32 s0, s2
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 ; GCN-NEXT: s_mov_b32 s1, s3
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 ; GCN-NEXT: s_mov_b32 s2, s4
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 ; GCN-NEXT: s_mov_b32 s3, s5
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 ; GCN-NEXT: s_mov_b32 s4, s6
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 ; GCN-NEXT: s_mov_b32 s5, s7
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 ; GCN-NEXT: s_mov_b32 s6, s8
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 ; GCN-NEXT: s_mov_b32 s7, s9
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 ; GCN-NEXT: s_mov_b32 s8, s10
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10 ; GCN-NEXT: s_mov_b32 s9, s11
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11 ; GCN-NEXT: s_mov_b32 s10, s12
; GCN: [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12 ; GCN-NEXT: s_mov_b32 s11, s13
; GCN: [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13 ; GCN-NEXT: image_sample_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf
; GCN: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GCN-NEXT: ; return to shader part epilog
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GCN: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32)
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.1d), 15, [[BUILD_VECTOR2]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GCN: $vgpr0 = COPY [[UV]](s32)
; GCN: $vgpr1 = COPY [[UV1]](s32)
; GCN: $vgpr2 = COPY [[UV2]](s32)
; GCN: $vgpr3 = COPY [[UV3]](s32)
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.l.1d.v4f32.f32(i32 15, float %zcompare, float %s, float -2.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.sample.c.l.1d.v4f32.f32(i32 15, float %zcompare, float %s, float -2.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
define amdgpu_ps <4 x float> @sample_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t, float %lod) { define amdgpu_ps <4 x float> @sample_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t, float %lod) {
; GCN-LABEL: name: sample_c_l_2d ; GCN-LABEL: sample_c_l_2d:
; GCN: bb.1.main_body: ; GCN: ; %bb.0: ; %main_body
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 ; GCN-NEXT: s_mov_b32 s0, s2
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 ; GCN-NEXT: s_mov_b32 s1, s3
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 ; GCN-NEXT: s_mov_b32 s2, s4
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 ; GCN-NEXT: s_mov_b32 s3, s5
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 ; GCN-NEXT: s_mov_b32 s4, s6
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 ; GCN-NEXT: s_mov_b32 s5, s7
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 ; GCN-NEXT: s_mov_b32 s6, s8
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 ; GCN-NEXT: s_mov_b32 s7, s9
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 ; GCN-NEXT: s_mov_b32 s8, s10
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10 ; GCN-NEXT: s_mov_b32 s9, s11
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11 ; GCN-NEXT: s_mov_b32 s10, s12
; GCN: [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12 ; GCN-NEXT: s_mov_b32 s11, s13
; GCN: [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13 ; GCN-NEXT: image_sample_c_lz v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf
; GCN: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GCN-NEXT: ; return to shader part epilog
; GCN: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GCN: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32)
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.2d), 15, [[BUILD_VECTOR2]](<3 x s32>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GCN: $vgpr0 = COPY [[UV]](s32)
; GCN: $vgpr1 = COPY [[UV1]](s32)
; GCN: $vgpr2 = COPY [[UV2]](s32)
; GCN: $vgpr3 = COPY [[UV3]](s32)
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.l.2d.v4f32.f32(i32 15, float %zcompare, float %s, float %t, float 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.sample.c.l.2d.v4f32.f32(i32 15, float %zcompare, float %s, float %t, float 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
define amdgpu_ps <4 x float> @sample_l_o_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %lod) { define amdgpu_ps <4 x float> @sample_l_o_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %lod) {
; GCN-LABEL: name: sample_l_o_1d ; GCN-LABEL: sample_l_o_1d:
; GCN: bb.1.main_body: ; GCN: ; %bb.0: ; %main_body
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1 ; GCN-NEXT: s_mov_b32 s0, s2
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 ; GCN-NEXT: s_mov_b32 s1, s3
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 ; GCN-NEXT: s_mov_b32 s2, s4
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 ; GCN-NEXT: s_mov_b32 s3, s5
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 ; GCN-NEXT: s_mov_b32 s4, s6
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 ; GCN-NEXT: s_mov_b32 s5, s7
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 ; GCN-NEXT: s_mov_b32 s6, s8
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 ; GCN-NEXT: s_mov_b32 s7, s9
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 ; GCN-NEXT: s_mov_b32 s8, s10
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10 ; GCN-NEXT: s_mov_b32 s9, s11
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11 ; GCN-NEXT: s_mov_b32 s10, s12
; GCN: [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12 ; GCN-NEXT: s_mov_b32 s11, s13
; GCN: [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13 ; GCN-NEXT: image_sample_lz_o v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf
; GCN: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GCN-NEXT: ; return to shader part epilog
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GCN: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32)
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.lz.o.1d), 15, [[BUILD_VECTOR2]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GCN: $vgpr0 = COPY [[UV]](s32)
; GCN: $vgpr1 = COPY [[UV1]](s32)
; GCN: $vgpr2 = COPY [[UV2]](s32)
; GCN: $vgpr3 = COPY [[UV3]](s32)
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.l.o.1d.v4f32.f32(i32 15, i32 %offset, float %s, float 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.sample.l.o.1d.v4f32.f32(i32 15, i32 %offset, float %s, float 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
define amdgpu_ps <4 x float> @sample_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %t, float %lod) { define amdgpu_ps <4 x float> @sample_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %t, float %lod) {
; GCN-LABEL: name: sample_l_o_2d ; GCN-LABEL: sample_l_o_2d:
; GCN: bb.1.main_body: ; GCN: ; %bb.0: ; %main_body
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 ; GCN-NEXT: s_mov_b32 s0, s2
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 ; GCN-NEXT: s_mov_b32 s1, s3
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 ; GCN-NEXT: s_mov_b32 s2, s4
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 ; GCN-NEXT: s_mov_b32 s3, s5
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 ; GCN-NEXT: s_mov_b32 s4, s6
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 ; GCN-NEXT: s_mov_b32 s5, s7
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 ; GCN-NEXT: s_mov_b32 s6, s8
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 ; GCN-NEXT: s_mov_b32 s7, s9
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 ; GCN-NEXT: s_mov_b32 s8, s10
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10 ; GCN-NEXT: s_mov_b32 s9, s11
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11 ; GCN-NEXT: s_mov_b32 s10, s12
; GCN: [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12 ; GCN-NEXT: s_mov_b32 s11, s13
; GCN: [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13 ; GCN-NEXT: image_sample_lz_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf
; GCN: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GCN-NEXT: ; return to shader part epilog
; GCN: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GCN: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32)
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.lz.o.2d), 15, [[BUILD_VECTOR2]](<3 x s32>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GCN: $vgpr0 = COPY [[UV]](s32)
; GCN: $vgpr1 = COPY [[UV1]](s32)
; GCN: $vgpr2 = COPY [[UV2]](s32)
; GCN: $vgpr3 = COPY [[UV3]](s32)
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.l.o.2d.v4f32.f32(i32 15, i32 %offset, float %s, float %t, float 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.sample.l.o.2d.v4f32.f32(i32 15, i32 %offset, float %s, float %t, float 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
define amdgpu_ps <4 x float> @sample_c_l_o_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %lod) { define amdgpu_ps <4 x float> @sample_c_l_o_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %lod) {
; GCN-LABEL: name: sample_c_l_o_1d ; GCN-LABEL: sample_c_l_o_1d:
; GCN: bb.1.main_body: ; GCN: ; %bb.0: ; %main_body
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 ; GCN-NEXT: s_mov_b32 s0, s2
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 ; GCN-NEXT: s_mov_b32 s1, s3
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 ; GCN-NEXT: s_mov_b32 s2, s4
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 ; GCN-NEXT: s_mov_b32 s3, s5
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 ; GCN-NEXT: s_mov_b32 s4, s6
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 ; GCN-NEXT: s_mov_b32 s5, s7
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 ; GCN-NEXT: s_mov_b32 s6, s8
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 ; GCN-NEXT: s_mov_b32 s7, s9
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 ; GCN-NEXT: s_mov_b32 s8, s10
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10 ; GCN-NEXT: s_mov_b32 s9, s11
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11 ; GCN-NEXT: s_mov_b32 s10, s12
; GCN: [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12 ; GCN-NEXT: s_mov_b32 s11, s13
; GCN: [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13 ; GCN-NEXT: image_sample_c_lz_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf
; GCN: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GCN-NEXT: ; return to shader part epilog
; GCN: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GCN: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32)
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.o.1d), 15, [[BUILD_VECTOR2]](<3 x s32>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GCN: $vgpr0 = COPY [[UV]](s32)
; GCN: $vgpr1 = COPY [[UV1]](s32)
; GCN: $vgpr2 = COPY [[UV2]](s32)
; GCN: $vgpr3 = COPY [[UV3]](s32)
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.l.o.1d.v4f32.f32(i32 15, i32 %offset, float %zcompare, float %s, float 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.sample.c.l.o.1d.v4f32.f32(i32 15, i32 %offset, float %zcompare, float %s, float 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
define amdgpu_ps <4 x float> @sample_c_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %t, float %lod) { define amdgpu_ps <4 x float> @sample_c_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %t, float %lod) {
; GCN-LABEL: name: sample_c_l_o_2d ; GCN-LABEL: sample_c_l_o_2d:
; GCN: bb.1.main_body: ; GCN: ; %bb.0: ; %main_body
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GCN-NEXT: s_mov_b32 s0, s2
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 ; GCN-NEXT: s_mov_b32 s1, s3
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 ; GCN-NEXT: s_mov_b32 s2, s4
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 ; GCN-NEXT: s_mov_b32 s3, s5
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 ; GCN-NEXT: s_mov_b32 s4, s6
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 ; GCN-NEXT: s_mov_b32 s5, s7
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 ; GCN-NEXT: s_mov_b32 s6, s8
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 ; GCN-NEXT: s_mov_b32 s7, s9
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 ; GCN-NEXT: s_mov_b32 s8, s10
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10 ; GCN-NEXT: s_mov_b32 s9, s11
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11 ; GCN-NEXT: s_mov_b32 s10, s12
; GCN: [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12 ; GCN-NEXT: s_mov_b32 s11, s13
; GCN: [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13 ; GCN-NEXT: image_sample_c_lz_o v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf
; GCN: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GCN-NEXT: ; return to shader part epilog
; GCN: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GCN: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GCN: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.sample.c.lz.o.2d), 15, [[BUILD_VECTOR2]](<4 x s32>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GCN: $vgpr0 = COPY [[UV]](s32)
; GCN: $vgpr1 = COPY [[UV1]](s32)
; GCN: $vgpr2 = COPY [[UV2]](s32)
; GCN: $vgpr3 = COPY [[UV3]](s32)
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.sample.c.l.o.2d.v4f32.f32(i32 15, i32 %offset, float %zcompare, float %s, float %t, float 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.sample.c.l.o.2d.v4f32.f32(i32 15, i32 %offset, float %zcompare, float %s, float %t, float 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
define amdgpu_ps <4 x float> @gather4_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %lod) { define amdgpu_ps <4 x float> @gather4_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t, float %lod) {
; GCN-LABEL: name: gather4_l_2d ; GCN-LABEL: gather4_l_2d:
; GCN: bb.1.main_body: ; GCN: ; %bb.0: ; %main_body
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1 ; GCN-NEXT: s_mov_b32 s0, s2
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 ; GCN-NEXT: s_mov_b32 s1, s3
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 ; GCN-NEXT: s_mov_b32 s2, s4
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 ; GCN-NEXT: s_mov_b32 s3, s5
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 ; GCN-NEXT: s_mov_b32 s4, s6
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 ; GCN-NEXT: s_mov_b32 s5, s7
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 ; GCN-NEXT: s_mov_b32 s6, s8
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 ; GCN-NEXT: s_mov_b32 s7, s9
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 ; GCN-NEXT: s_mov_b32 s8, s10
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10 ; GCN-NEXT: s_mov_b32 s9, s11
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11 ; GCN-NEXT: s_mov_b32 s10, s12
; GCN: [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12 ; GCN-NEXT: s_mov_b32 s11, s13
; GCN: [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13 ; GCN-NEXT: image_gather4_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0xf
; GCN: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GCN-NEXT: ; return to shader part epilog
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GCN: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32)
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.lz.2d), 15, [[BUILD_VECTOR2]](<2 x s32>), $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GCN: $vgpr0 = COPY [[UV]](s32)
; GCN: $vgpr1 = COPY [[UV1]](s32)
; GCN: $vgpr2 = COPY [[UV2]](s32)
; GCN: $vgpr3 = COPY [[UV3]](s32)
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f32(i32 15, float %s, float %t, float 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.gather4.l.2d.v4f32.f32(i32 15, float %s, float %t, float 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
define amdgpu_ps <4 x float> @gather4_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t, float %lod) { define amdgpu_ps <4 x float> @gather4_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s, float %t, float %lod) {
; GCN-LABEL: name: gather4_c_l_2d ; GCN-LABEL: gather4_c_l_2d:
; GCN: bb.1.main_body: ; GCN: ; %bb.0: ; %main_body
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 ; GCN-NEXT: s_mov_b32 s0, s2
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 ; GCN-NEXT: s_mov_b32 s1, s3
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 ; GCN-NEXT: s_mov_b32 s2, s4
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 ; GCN-NEXT: s_mov_b32 s3, s5
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 ; GCN-NEXT: s_mov_b32 s4, s6
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 ; GCN-NEXT: s_mov_b32 s5, s7
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 ; GCN-NEXT: s_mov_b32 s6, s8
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 ; GCN-NEXT: s_mov_b32 s7, s9
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 ; GCN-NEXT: s_mov_b32 s8, s10
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10 ; GCN-NEXT: s_mov_b32 s9, s11
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11 ; GCN-NEXT: s_mov_b32 s10, s12
; GCN: [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12 ; GCN-NEXT: s_mov_b32 s11, s13
; GCN: [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13 ; GCN-NEXT: image_gather4_c_lz v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf
; GCN: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GCN-NEXT: ; return to shader part epilog
; GCN: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GCN: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32)
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.lz.2d), 15, [[BUILD_VECTOR2]](<3 x s32>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GCN: $vgpr0 = COPY [[UV]](s32)
; GCN: $vgpr1 = COPY [[UV1]](s32)
; GCN: $vgpr2 = COPY [[UV2]](s32)
; GCN: $vgpr3 = COPY [[UV3]](s32)
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.2d.v4f32.f32(i32 15, float %zcompare, float %s, float %t, float 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.2d.v4f32.f32(i32 15, float %zcompare, float %s, float %t, float 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
define amdgpu_ps <4 x float> @gather4_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %t, float %lod) { define amdgpu_ps <4 x float> @gather4_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %s, float %t, float %lod) {
; GCN-LABEL: name: gather4_l_o_2d ; GCN-LABEL: gather4_l_o_2d:
; GCN: bb.1.main_body: ; GCN: ; %bb.0: ; %main_body
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 ; GCN-NEXT: s_mov_b32 s0, s2
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 ; GCN-NEXT: s_mov_b32 s1, s3
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 ; GCN-NEXT: s_mov_b32 s2, s4
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 ; GCN-NEXT: s_mov_b32 s3, s5
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 ; GCN-NEXT: s_mov_b32 s4, s6
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 ; GCN-NEXT: s_mov_b32 s5, s7
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 ; GCN-NEXT: s_mov_b32 s6, s8
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 ; GCN-NEXT: s_mov_b32 s7, s9
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 ; GCN-NEXT: s_mov_b32 s8, s10
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10 ; GCN-NEXT: s_mov_b32 s9, s11
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11 ; GCN-NEXT: s_mov_b32 s10, s12
; GCN: [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12 ; GCN-NEXT: s_mov_b32 s11, s13
; GCN: [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13 ; GCN-NEXT: image_gather4_lz_o v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf
; GCN: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GCN-NEXT: ; return to shader part epilog
; GCN: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GCN: [[BUILD_VECTOR2:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32)
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.lz.o.2d), 15, [[BUILD_VECTOR2]](<3 x s32>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GCN: $vgpr0 = COPY [[UV]](s32)
; GCN: $vgpr1 = COPY [[UV1]](s32)
; GCN: $vgpr2 = COPY [[UV2]](s32)
; GCN: $vgpr3 = COPY [[UV3]](s32)
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.l.o.2d.v4f32.f32(i32 15, i32 %offset, float %s, float %t, float 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.gather4.l.o.2d.v4f32.f32(i32 15, i32 %offset, float %s, float %t, float 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v
} }
define amdgpu_ps <4 x float> @gather4_c_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %t, float %lod) { define amdgpu_ps <4 x float> @gather4_c_l_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %s, float %t, float %lod) {
; GCN-LABEL: name: gather4_c_l_o_2d ; GCN-LABEL: gather4_c_l_o_2d:
; GCN: bb.1.main_body: ; GCN: ; %bb.0: ; %main_body
; GCN: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GCN-NEXT: s_mov_b32 s0, s2
; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr2 ; GCN-NEXT: s_mov_b32 s1, s3
; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr3 ; GCN-NEXT: s_mov_b32 s2, s4
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr4 ; GCN-NEXT: s_mov_b32 s3, s5
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr5 ; GCN-NEXT: s_mov_b32 s4, s6
; GCN: [[COPY4:%[0-9]+]]:_(s32) = COPY $sgpr6 ; GCN-NEXT: s_mov_b32 s5, s7
; GCN: [[COPY5:%[0-9]+]]:_(s32) = COPY $sgpr7 ; GCN-NEXT: s_mov_b32 s6, s8
; GCN: [[COPY6:%[0-9]+]]:_(s32) = COPY $sgpr8 ; GCN-NEXT: s_mov_b32 s7, s9
; GCN: [[COPY7:%[0-9]+]]:_(s32) = COPY $sgpr9 ; GCN-NEXT: s_mov_b32 s8, s10
; GCN: [[COPY8:%[0-9]+]]:_(s32) = COPY $sgpr10 ; GCN-NEXT: s_mov_b32 s9, s11
; GCN: [[COPY9:%[0-9]+]]:_(s32) = COPY $sgpr11 ; GCN-NEXT: s_mov_b32 s10, s12
; GCN: [[COPY10:%[0-9]+]]:_(s32) = COPY $sgpr12 ; GCN-NEXT: s_mov_b32 s11, s13
; GCN: [[COPY11:%[0-9]+]]:_(s32) = COPY $sgpr13 ; GCN-NEXT: image_gather4_c_lz_o v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf
; GCN: [[COPY12:%[0-9]+]]:_(s32) = COPY $vgpr0 ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN: [[COPY13:%[0-9]+]]:_(s32) = COPY $vgpr1 ; GCN-NEXT: ; return to shader part epilog
; GCN: [[COPY14:%[0-9]+]]:_(s32) = COPY $vgpr2
; GCN: [[COPY15:%[0-9]+]]:_(s32) = COPY $vgpr3
; GCN: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32)
; GCN: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32)
; GCN: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32)
; GCN: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x s32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.gather4.c.lz.o.2d), 15, [[BUILD_VECTOR2]](<4 x s32>), $noreg, $noreg, $noreg, [[BUILD_VECTOR]](<8 x s32>), [[BUILD_VECTOR1]](<4 x s32>), 0, 0, 0 :: (dereferenceable load 16 from custom "TargetCustom8")
; GCN: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32), [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x s32>)
; GCN: $vgpr0 = COPY [[UV]](s32)
; GCN: $vgpr1 = COPY [[UV1]](s32)
; GCN: $vgpr2 = COPY [[UV2]](s32)
; GCN: $vgpr3 = COPY [[UV3]](s32)
; GCN: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3
main_body: main_body:
%v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.o.2d.v4f32.f32(i32 15, i32 %offset, float %zcompare, float %s, float %t, float 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0) %v = call <4 x float> @llvm.amdgcn.image.gather4.c.l.o.2d.v4f32.f32(i32 15, i32 %offset, float %zcompare, float %s, float %t, float 0.000000e+00, <8 x i32> %rsrc, <4 x i32> %samp, i1 false, i32 0, i32 0)
ret <4 x float> %v ret <4 x float> %v