forked from OSchip/llvm-project
[Builtin][ARM] Add Thumb1 support for aeabi_c{f,d}cmp.S and dcmp.S
Reviewers: compnerd, rengolin Reviewed By: rengolin Subscribers: aemerson, llvm-commits, mgorny Differential Revision: https://reviews.llvm.org/D28985 llvm-svn: 293247
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@ -328,8 +328,11 @@ set(arm_EABI_SOURCES
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arm/aeabi_uldivmod.S)
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set(thumb1_EABI_SOURCES
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arm/aeabi_cdcmp.S
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arm/aeabi_cdcmpeq_check_nan.c
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arm/aeabi_cfcmp.S
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arm/aeabi_cfcmpeq_check_nan.c
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arm/aeabi_dcmp.S
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arm/aeabi_div0.c
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arm/aeabi_drsub.c
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arm/aeabi_fcmp.S
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@ -30,6 +30,19 @@ DEFINE_COMPILERRT_FUNCTION(__aeabi_cdcmpeq)
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push {r0-r3, lr}
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bl __aeabi_cdcmpeq_check_nan
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cmp r0, #1
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#if __ARM_ARCH_ISA_THUMB == 1
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beq 1f
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// NaN has been ruled out, so __aeabi_cdcmple can't trap
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mov r0, sp
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ldm r0, {r0-r3}
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bl __aeabi_cdcmple
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pop {r0-r3, pc}
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1:
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// Z = 0, C = 1
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movs r0, #0xF
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lsls r0, r0, #31
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pop {r0-r3, pc}
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#else
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pop {r0-r3, lr}
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// NaN has been ruled out, so __aeabi_cdcmple can't trap
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@ -37,6 +50,7 @@ DEFINE_COMPILERRT_FUNCTION(__aeabi_cdcmpeq)
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msr CPSR_f, #APSR_C
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JMP(lr)
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#endif
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END_COMPILERRT_FUNCTION(__aeabi_cdcmpeq)
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@ -59,6 +73,28 @@ DEFINE_COMPILERRT_FUNCTION(__aeabi_cdcmple)
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bl __aeabi_dcmplt
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cmp r0, #1
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#if __ARM_ARCH_ISA_THUMB == 1
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bne 1f
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// Z = 0, C = 0
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movs r0, #1
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lsls r0, r0, #1
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pop {r0-r3, pc}
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1:
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mov r0, sp
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ldm r0, {r0-r3}
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bl __aeabi_dcmpeq
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cmp r0, #1
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bne 2f
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// Z = 1, C = 1
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movs r0, #2
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lsls r0, r0, #31
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pop {r0-r3, pc}
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2:
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// Z = 0, C = 1
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movs r0, #0xF
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lsls r0, r0, #31
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pop {r0-r3, pc}
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#else
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moveq ip, #0
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beq 1f
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@ -72,6 +108,7 @@ DEFINE_COMPILERRT_FUNCTION(__aeabi_cdcmple)
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msr CPSR_f, ip
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pop {r0-r3}
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POP_PC()
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#endif
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END_COMPILERRT_FUNCTION(__aeabi_cdcmple)
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// int __aeabi_cdrcmple(double a, double b) {
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@ -30,6 +30,19 @@ DEFINE_COMPILERRT_FUNCTION(__aeabi_cfcmpeq)
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push {r0-r3, lr}
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bl __aeabi_cfcmpeq_check_nan
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cmp r0, #1
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#if __ARM_ARCH_ISA_THUMB == 1
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beq 1f
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// NaN has been ruled out, so __aeabi_cfcmple can't trap
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mov r0, sp
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ldm r0, {r0-r3}
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bl __aeabi_cfcmple
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pop {r0-r3, pc}
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1:
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// Z = 0, C = 1
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movs r0, #0xF
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lsls r0, r0, #31
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pop {r0-r3, pc}
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#else
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pop {r0-r3, lr}
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// NaN has been ruled out, so __aeabi_cfcmple can't trap
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@ -37,6 +50,7 @@ DEFINE_COMPILERRT_FUNCTION(__aeabi_cfcmpeq)
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msr CPSR_f, #APSR_C
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JMP(lr)
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#endif
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END_COMPILERRT_FUNCTION(__aeabi_cfcmpeq)
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@ -59,6 +73,28 @@ DEFINE_COMPILERRT_FUNCTION(__aeabi_cfcmple)
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bl __aeabi_fcmplt
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cmp r0, #1
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#if __ARM_ARCH_ISA_THUMB == 1
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bne 1f
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// Z = 0, C = 0
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movs r0, #1
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lsls r0, r0, #1
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pop {r0-r3, pc}
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1:
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mov r0, sp
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ldm r0, {r0-r3}
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bl __aeabi_fcmpeq
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cmp r0, #1
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bne 2f
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// Z = 1, C = 1
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movs r0, #2
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lsls r0, r0, #31
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pop {r0-r3, pc}
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2:
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// Z = 0, C = 1
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movs r0, #0xF
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lsls r0, r0, #31
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pop {r0-r3, pc}
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#else
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moveq ip, #0
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beq 1f
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@ -72,6 +108,7 @@ DEFINE_COMPILERRT_FUNCTION(__aeabi_cfcmple)
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msr CPSR_f, ip
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pop {r0-r3}
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POP_PC()
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#endif
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END_COMPILERRT_FUNCTION(__aeabi_cfcmple)
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// int __aeabi_cfrcmple(float a, float b) {
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@ -26,10 +26,10 @@ DEFINE_COMPILERRT_FUNCTION(__aeabi_dcmp ## cond) \
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bl SYMBOL_NAME(__ ## cond ## df2) SEPARATOR \
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cmp r0, #0 SEPARATOR \
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b ## cond 1f SEPARATOR \
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mov r0, #0 SEPARATOR \
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movs r0, #0 SEPARATOR \
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pop { r4, pc } SEPARATOR \
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1: SEPARATOR \
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mov r0, #1 SEPARATOR \
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movs r0, #1 SEPARATOR \
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pop { r4, pc } SEPARATOR \
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END_COMPILERRT_FUNCTION(__aeabi_dcmp ## cond)
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