forked from OSchip/llvm-project
[LegalizeTypes] In SoftenFloatRes_FNEG, always generate integer arithmetic, never fall back to using fsub.
We would previously fallback if the type wasn't f32/f64/f128. But I don't think any of the other floating point types ever go through the softening code anyway. So this code is dead.
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@ -452,25 +452,10 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FNEG(SDNode *N) {
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EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
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SDLoc dl(N);
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EVT FloatVT = N->getValueType(0);
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if (FloatVT == MVT::f32 || FloatVT == MVT::f64 || FloatVT == MVT::f128) {
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// Expand Y = FNEG(X) -> Y = X ^ sign mask
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APInt SignMask = APInt::getSignMask(NVT.getSizeInBits());
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return DAG.getNode(ISD::XOR, dl, NVT, GetSoftenedFloat(N->getOperand(0)),
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DAG.getConstant(SignMask, dl, NVT));
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}
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// Expand Y = FNEG(X) -> Y = SUB -0.0, X
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SDValue Ops[2] = { DAG.getConstantFP(-0.0, dl, N->getValueType(0)),
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GetSoftenedFloat(N->getOperand(0)) };
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TargetLowering::MakeLibCallOptions CallOptions;
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return TLI.makeLibCall(DAG, GetFPLibCall(N->getValueType(0),
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RTLIB::SUB_F32,
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RTLIB::SUB_F64,
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RTLIB::SUB_F80,
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RTLIB::SUB_F128,
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RTLIB::SUB_PPCF128),
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NVT, Ops, CallOptions, dl).first;
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// Expand Y = FNEG(X) -> Y = X ^ sign mask
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APInt SignMask = APInt::getSignMask(NVT.getSizeInBits());
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return DAG.getNode(ISD::XOR, dl, NVT, GetSoftenedFloat(N->getOperand(0)),
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DAG.getConstant(SignMask, dl, NVT));
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}
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SDValue DAGTypeLegalizer::SoftenFloatRes_FP_EXTEND(SDNode *N) {
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