forked from OSchip/llvm-project
[ARM GlobalISel] Cleanup CallLowering a bit
We never actually use the Offsets produced by ComputeValueVTs, so remove them until we need them. llvm-svn: 361755
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@ -192,8 +192,7 @@ void ARMCallLowering::splitToValueTypes(
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const Function &F = MF.getFunction();
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SmallVector<EVT, 4> SplitVTs;
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SmallVector<uint64_t, 4> Offsets;
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ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, &Offsets, 0);
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ComputeValueVTs(TLI, DL, OrigArg.Ty, SplitVTs, nullptr, nullptr, 0);
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if (SplitVTs.size() == 1) {
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// Even if there is no splitting to do, we still want to replace the
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@ -206,7 +205,6 @@ void ARMCallLowering::splitToValueTypes(
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return;
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}
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unsigned FirstRegIdx = SplitArgs.size();
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for (unsigned i = 0, e = SplitVTs.size(); i != e; ++i) {
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EVT SplitVT = SplitVTs[i];
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Type *SplitTy = SplitVT.getTypeForEVT(Ctx);
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@ -224,13 +222,11 @@ void ARMCallLowering::splitToValueTypes(
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Flags.setInConsecutiveRegsLast();
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}
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SplitArgs.push_back(
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ArgInfo{MRI.createGenericVirtualRegister(getLLTForType(*SplitTy, DL)),
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SplitTy, Flags, OrigArg.IsFixed});
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unsigned PartReg =
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MRI.createGenericVirtualRegister(getLLTForType(*SplitTy, DL));
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SplitArgs.push_back(ArgInfo{PartReg, SplitTy, Flags, OrigArg.IsFixed});
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PerformArgSplit(PartReg);
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}
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for (unsigned i = 0; i < Offsets.size(); ++i)
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PerformArgSplit(SplitArgs[FirstRegIdx + i].Reg, Offsets[i] * 8);
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}
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/// Lower the return value for the already existing \p Ret. This assumes that
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@ -262,9 +258,8 @@ bool ARMCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
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setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
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SmallVector<unsigned, 4> Regs;
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splitToValueTypes(
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CurArgInfo, SplitVTs, MF,
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[&](unsigned Reg, uint64_t Offset) { Regs.push_back(Reg); });
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splitToValueTypes(CurArgInfo, SplitVTs, MF,
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[&](unsigned Reg) { Regs.push_back(Reg); });
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if (Regs.size() > 1)
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MIRBuilder.buildUnmerge(Regs, VRegs[i]);
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}
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@ -466,9 +461,8 @@ bool ARMCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
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SplitRegs.clear();
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splitToValueTypes(AInfo, ArgInfos, MF, [&](unsigned Reg, uint64_t Offset) {
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SplitRegs.push_back(Reg);
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});
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splitToValueTypes(AInfo, ArgInfos, MF,
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[&](unsigned Reg) { SplitRegs.push_back(Reg); });
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if (!SplitRegs.empty())
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MIRBuilder.buildMerge(VRegs[Idx], SplitRegs);
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@ -575,9 +569,8 @@ bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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return false;
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SmallVector<unsigned, 8> Regs;
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splitToValueTypes(Arg, ArgInfos, MF, [&](unsigned Reg, uint64_t Offset) {
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Regs.push_back(Reg);
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});
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splitToValueTypes(Arg, ArgInfos, MF,
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[&](unsigned Reg) { Regs.push_back(Reg); });
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if (Regs.size() > 1)
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MIRBuilder.buildUnmerge(Regs, Arg.Reg);
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@ -598,9 +591,7 @@ bool ARMCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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ArgInfos.clear();
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SmallVector<unsigned, 8> SplitRegs;
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splitToValueTypes(OrigRet, ArgInfos, MF,
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[&](unsigned Reg, uint64_t Offset) {
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SplitRegs.push_back(Reg);
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});
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[&](unsigned Reg) { SplitRegs.push_back(Reg); });
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auto RetAssignFn = TLI.CCAssignFnForReturn(CallConv, IsVarArg);
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CallReturnHandler RetHandler(MIRBuilder, MRI, MIB, RetAssignFn);
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@ -47,7 +47,7 @@ private:
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ArrayRef<unsigned> VRegs,
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MachineInstrBuilder &Ret) const;
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using SplitArgTy = std::function<void(unsigned Reg, uint64_t Offset)>;
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using SplitArgTy = std::function<void(unsigned Reg)>;
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/// Split an argument into one or more arguments that the CC lowering can cope
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/// with (e.g. replace pointers with integers).
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