From 68a8efa374740a0829e77f57c8a2b13bead85d7f Mon Sep 17 00:00:00 2001 From: Ahmed Bougacha Date: Tue, 2 Feb 2016 01:44:03 +0000 Subject: [PATCH] [X86][FastISel] Don't force Nearest-Even rounding for VCVTPS2PH, use MXCSR. FastISel counterpart to r259448. llvm-svn: 259449 --- llvm/lib/Target/X86/X86FastISel.cpp | 6 ++++-- llvm/test/CodeGen/X86/fast-isel-float-half-convertion.ll | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp index f48b47934e03..854a4e7932eb 100644 --- a/llvm/lib/Target/X86/X86FastISel.cpp +++ b/llvm/lib/Target/X86/X86FastISel.cpp @@ -2294,8 +2294,10 @@ bool X86FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) { // register class VR128 by method 'constrainOperandRegClass' which is // directly called by 'fastEmitInst_ri'. // Instruction VCVTPS2PHrr takes an extra immediate operand which is - // used to provide rounding control. - InputReg = fastEmitInst_ri(X86::VCVTPS2PHrr, RC, InputReg, false, 0); + // used to provide rounding control: use MXCSR.RC, encoded as 0b100. + // It's consistent with the other FP instructions, which are usually + // controlled by MXCSR. + InputReg = fastEmitInst_ri(X86::VCVTPS2PHrr, RC, InputReg, false, 4); // Move the lower 32-bits of ResultReg to another register of class GR32. ResultReg = createResultReg(&X86::GR32RegClass); diff --git a/llvm/test/CodeGen/X86/fast-isel-float-half-convertion.ll b/llvm/test/CodeGen/X86/fast-isel-float-half-convertion.ll index 707a325bf41d..acb85fd171f5 100644 --- a/llvm/test/CodeGen/X86/fast-isel-float-half-convertion.ll +++ b/llvm/test/CodeGen/X86/fast-isel-float-half-convertion.ll @@ -4,7 +4,7 @@ define i16 @test_fp32_to_fp16(float %a) { ; CHECK-LABEL: test_fp32_to_fp16: -; CHECK: vcvtps2ph $0, %xmm0, %xmm0 +; CHECK: vcvtps2ph $4, %xmm0, %xmm0 ; CHECK-NEXT: vmovd %xmm0, %eax ; CHECK-NEXT: retq entry: