maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[X86] Remove mask parameter from vpshufbitqmb intrinsics. Change result to a vXi1 vector. 

We'll do the scalar<->vXi1 conversions with bitcasts in IR.

Fixes PR40258

llvm-svn: 351029
This commit is contained in:
Craig Topper 2019-01-14 00:03:55 +00:00
parent 3f3b8ef442
commit 689b3b71af
3 changed files with 34 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
clang/lib/CodeGen/CGBuiltin.cpp
View File

@ -11152,6 +11152,31 @@ Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID,
return EmitX86MaskedCompareResult(*this, Fpclass, NumElts, MaskIn);
}
case X86::BI__builtin_ia32_vpshufbitqmb128_mask:
case X86::BI__builtin_ia32_vpshufbitqmb256_mask:
case X86::BI__builtin_ia32_vpshufbitqmb512_mask: {
unsigned NumElts = Ops[0]->getType()->getVectorNumElements();
Value *MaskIn = Ops[2];
Ops.erase(&Ops[2]);
Intrinsic::ID ID;
switch (BuiltinID) {
default: llvm_unreachable("Unsupported intrinsic!");
case X86::BI__builtin_ia32_vpshufbitqmb128_mask:
ID = Intrinsic::x86_avx512_vpshufbitqmb_128;
break;
case X86::BI__builtin_ia32_vpshufbitqmb256_mask:
ID = Intrinsic::x86_avx512_vpshufbitqmb_256;
break;
case X86::BI__builtin_ia32_vpshufbitqmb512_mask:
ID = Intrinsic::x86_avx512_vpshufbitqmb_512;
break;
}
Value *Fpclass = Builder.CreateCall(CGM.getIntrinsic(ID), Ops);
return EmitX86MaskedCompareResult(*this, Fpclass, NumElts, MaskIn);
}
// packed comparison intrinsics
case X86::BI__builtin_ia32_cmpeqps:
case X86::BI__builtin_ia32_cmpeqpd:

5
clang/test/CodeGen/avx512bitalg-builtins.c
View File

@ -42,13 +42,14 @@ __m512i test_mm512_maskz_popcnt_epi8(__mmask64 __U, __m512i __B) {
__mmask64 test_mm512_mask_bitshuffle_epi64_mask(__mmask64 __U, __m512i __A, __m512i __B) {
// CHECK-LABEL: @test_mm512_mask_bitshuffle_epi64_mask
// CHECK: @llvm.x86.avx512.mask.vpshufbitqmb.512
// CHECK: @llvm.x86.avx512.vpshufbitqmb.512
// CHECK: and <64 x i1> %{{.*}}, %{{.*}}
return _mm512_mask_bitshuffle_epi64_mask(__U, __A, __B);
}
__mmask64 test_mm512_bitshuffle_epi64_mask(__m512i __A, __m512i __B) {
// CHECK-LABEL: @test_mm512_bitshuffle_epi64_mask
// CHECK: @llvm.x86.avx512.mask.vpshufbitqmb.512
// CHECK: @llvm.x86.avx512.vpshufbitqmb.512
return _mm512_bitshuffle_epi64_mask(__A, __B);
}

10
clang/test/CodeGen/avx512vlbitalg-builtins.c
View File

@ -80,25 +80,27 @@ __m128i test_mm_maskz_popcnt_epi8(__mmask16 __U, __m128i __B) {
__mmask32 test_mm256_mask_bitshuffle_epi64_mask(__mmask32 __U, __m256i __A, __m256i __B) {
// CHECK-LABEL: @test_mm256_mask_bitshuffle_epi64_mask
// CHECK: @llvm.x86.avx512.mask.vpshufbitqmb.256
// CHECK: @llvm.x86.avx512.vpshufbitqmb.256
// CHECK: and <32 x i1> %{{.*}}, %{{.*}}
return _mm256_mask_bitshuffle_epi64_mask(__U, __A, __B);
}
__mmask32 test_mm256_bitshuffle_epi64_mask(__m256i __A, __m256i __B) {
// CHECK-LABEL: @test_mm256_bitshuffle_epi64_mask
// CHECK: @llvm.x86.avx512.mask.vpshufbitqmb.256
// CHECK: @llvm.x86.avx512.vpshufbitqmb.256
return _mm256_bitshuffle_epi64_mask(__A, __B);
}
__mmask16 test_mm_mask_bitshuffle_epi64_mask(__mmask16 __U, __m128i __A, __m128i __B) {
// CHECK-LABEL: @test_mm_mask_bitshuffle_epi64_mask
// CHECK: @llvm.x86.avx512.mask.vpshufbitqmb.128
// CHECK: @llvm.x86.avx512.vpshufbitqmb.128
// CHECK: and <16 x i1> %{{.*}}, %{{.*}}
return _mm_mask_bitshuffle_epi64_mask(__U, __A, __B);
}
__mmask16 test_mm_bitshuffle_epi64_mask(__m128i __A, __m128i __B) {
// CHECK-LABEL: @test_mm_bitshuffle_epi64_mask
// CHECK: @llvm.x86.avx512.mask.vpshufbitqmb.128
// CHECK: @llvm.x86.avx512.vpshufbitqmb.128
return _mm_bitshuffle_epi64_mask(__A, __B);
}