forked from OSchip/llvm-project
Break scheduling infrastructure out of TargetMachine.cpp into SchedInfo.cpp
llvm-svn: 569
This commit is contained in:
Chris Lattner
parent
374e3563c1
commit
6875e9cc97
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@ -0,0 +1,175 @@
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//===-- SchedInfo.cpp - Generic code to support target schedulers ----------==//
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//
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// This file implements the generic part of a Scheduler description for a
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// target. This functionality is defined in the llvm/Target/SchedInfo.h file.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/SchedInfo.h"
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// External object describing the machine instructions
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// Initialized only when the TargetMachine class is created
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// and reset when that class is destroyed.
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//
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const MachineInstrDescriptor* TargetInstrDescriptors = 0;
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resourceId_t MachineResource::nextId = 0;
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// Check if fromRVec and toRVec have *any* common entries.
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// Assume the vectors are sorted in increasing order.
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// Algorithm copied from function set_intersection() for sorted ranges
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// (stl_algo.h).
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//
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inline static bool RUConflict(const vector<resourceId_t>& fromRVec,
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const vector<resourceId_t>& toRVec) {
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unsigned fN = fromRVec.size(), tN = toRVec.size();
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unsigned fi = 0, ti = 0;
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while (fi < fN && ti < tN) {
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if (fromRVec[fi] < toRVec[ti])
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++fi;
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else if (toRVec[ti] < fromRVec[fi])
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++ti;
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else
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return true;
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}
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return false;
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}
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static cycles_t ComputeMinGap(const InstrRUsage &fromRU,
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const InstrRUsage &toRU) {
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cycles_t minGap = 0;
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if (fromRU.numBubbles > 0)
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minGap = fromRU.numBubbles;
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if (minGap < fromRU.numCycles) {
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// only need to check from cycle `minGap' onwards
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for (cycles_t gap=minGap; gap <= fromRU.numCycles-1; gap++) {
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// check if instr. #2 can start executing `gap' cycles after #1
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// by checking for resource conflicts in each overlapping cycle
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cycles_t numOverlap = min(fromRU.numCycles - gap, toRU.numCycles);
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for (cycles_t c = 0; c <= numOverlap-1; c++)
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if (RUConflict(fromRU.resourcesByCycle[gap + c],
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toRU.resourcesByCycle[c])) {
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// conflict found so minGap must be more than `gap'
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minGap = gap+1;
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break;
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}
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}
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}
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return minGap;
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}
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//---------------------------------------------------------------------------
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// class MachineSchedInfo
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// Interface to machine description for instruction scheduling
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//---------------------------------------------------------------------------
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MachineSchedInfo::MachineSchedInfo(int NumSchedClasses,
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const MachineInstrInfo* Mii,
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const InstrClassRUsage* ClassRUsages,
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const InstrRUsageDelta* UsageDeltas,
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const InstrIssueDelta* IssueDeltas,
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unsigned int NumUsageDeltas,
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unsigned int NumIssueDeltas)
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: numSchedClasses(NumSchedClasses), mii(Mii),
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classRUsages(ClassRUsages), usageDeltas(UsageDeltas),
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issueDeltas(IssueDeltas), numUsageDeltas(NumUsageDeltas),
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numIssueDeltas(NumIssueDeltas) {
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}
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void MachineSchedInfo::initializeResources() {
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assert(MAX_NUM_SLOTS >= (int)getMaxNumIssueTotal()
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&& "Insufficient slots for static data! Increase MAX_NUM_SLOTS");
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// First, compute common resource usage info for each class because
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// most instructions will probably behave the same as their class.
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// Cannot allocate a vector of InstrRUsage so new each one.
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//
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vector<InstrRUsage> instrRUForClasses;
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instrRUForClasses.resize(numSchedClasses);
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for (InstrSchedClass sc = 0; sc < numSchedClasses; sc++) {
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// instrRUForClasses.push_back(new InstrRUsage);
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instrRUForClasses[sc].setMaxSlots(getMaxNumIssueTotal());
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instrRUForClasses[sc] = classRUsages[sc];
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}
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computeInstrResources(instrRUForClasses);
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computeIssueGaps(instrRUForClasses);
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}
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void MachineSchedInfo::computeInstrResources(
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const vector<InstrRUsage> &instrRUForClasses) {
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int numOpCodes = mii->getNumRealOpCodes();
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instrRUsages.resize(numOpCodes);
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// First get the resource usage information from the class resource usages.
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for (MachineOpCode op = 0; op < numOpCodes; ++op) {
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InstrSchedClass sc = getSchedClass(op);
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assert(sc >= 0 && sc < numSchedClasses);
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instrRUsages[op] = instrRUForClasses[sc];
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}
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// Now, modify the resource usages as specified in the deltas.
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for (unsigned i = 0; i < numUsageDeltas; ++i) {
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MachineOpCode op = usageDeltas[i].opCode;
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assert(op < numOpCodes);
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instrRUsages[op].addUsageDelta(usageDeltas[i]);
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}
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// Then modify the issue restrictions as specified in the deltas.
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for (unsigned i = 0; i < numIssueDeltas; ++i) {
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MachineOpCode op = issueDeltas[i].opCode;
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assert(op < numOpCodes);
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instrRUsages[issueDeltas[i].opCode].addIssueDelta(issueDeltas[i]);
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}
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}
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void MachineSchedInfo::computeIssueGaps(
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const vector<InstrRUsage> &instrRUForClasses) {
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int numOpCodes = mii->getNumRealOpCodes();
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instrRUsages.resize(numOpCodes);
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assert(numOpCodes < (1 << MAX_OPCODE_SIZE) - 1
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&& "numOpCodes invalid for implementation of class OpCodePair!");
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// First, compute issue gaps between pairs of classes based on common
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// resources usages for each class, because most instruction pairs will
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// usually behave the same as their class.
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//
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int classPairGaps[numSchedClasses][numSchedClasses];
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for (InstrSchedClass fromSC=0; fromSC < numSchedClasses; fromSC++)
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for (InstrSchedClass toSC=0; toSC < numSchedClasses; toSC++) {
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int classPairGap = ComputeMinGap(instrRUForClasses[fromSC],
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instrRUForClasses[toSC]);
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classPairGaps[fromSC][toSC] = classPairGap;
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}
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// Now, for each pair of instructions, use the class pair gap if both
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// instructions have identical resource usage as their respective classes.
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// If not, recompute the gap for the pair from scratch.
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longestIssueConflict = 0;
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for (MachineOpCode fromOp=0; fromOp < numOpCodes; fromOp++)
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for (MachineOpCode toOp=0; toOp < numOpCodes; toOp++) {
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int instrPairGap =
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(instrRUsages[fromOp].sameAsClass && instrRUsages[toOp].sameAsClass)
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? classPairGaps[getSchedClass(fromOp)][getSchedClass(toOp)]
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: ComputeMinGap(instrRUsages[fromOp], instrRUsages[toOp]);
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if (instrPairGap > 0) {
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issueGaps[OpCodePair(fromOp,toOp)] = instrPairGap;
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conflictLists[fromOp].push_back(toOp);
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longestIssueConflict = max(longestIssueConflict, instrPairGap);
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}
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}
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}
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@ -1,27 +1,13 @@
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//===-- TargetMachine.cpp - General Target Information ---------------------==//
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//
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// This file describes the general parts of a Target machine.
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// This file also implements the InstInfo interface as well...
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/SchedInfo.h"
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#include "llvm/Target/Machine.h"
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#include "llvm/Target/InstInfo.h"
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#include "llvm/DerivedTypes.h"
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// External object describing the machine instructions
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// Initialized only when the TargetMachine class is created
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// and reset when that class is destroyed.
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//
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const MachineInstrDescriptor* TargetInstrDescriptors = NULL;
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resourceId_t MachineResource::nextId = 0;
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static cycles_t ComputeMinGap (const InstrRUsage& fromRU,
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const InstrRUsage& toRU);
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static bool RUConflict (const vector<resourceId_t>& fromRVec,
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const vector<resourceId_t>& fromRVec);
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//---------------------------------------------------------------------------
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// class TargetMachine
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//
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@ -30,7 +16,6 @@ static bool RUConflict (const vector<resourceId_t>& fromRVec,
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//
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//---------------------------------------------------------------------------
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// function TargetMachine::findOptimalStorageSize
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//
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// Purpose:
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@ -70,9 +55,7 @@ MachineInstrInfo::MachineInstrInfo(const MachineInstrDescriptor* _desc,
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}
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/*dtor*/
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MachineInstrInfo::~MachineInstrInfo()
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{
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MachineInstrInfo::~MachineInstrInfo() {
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TargetInstrDescriptors = NULL; // reset global variable
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}
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@ -83,198 +66,13 @@ MachineInstrInfo::constantFitsInImmedField(MachineOpCode opCode,
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{
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// First, check if opCode has an immed field.
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bool isSignExtended;
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uint64_t maxImmedValue = this->maxImmedConstant(opCode, isSignExtended);
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if (maxImmedValue != 0)
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{
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// Now check if the constant fits
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if (intValue <= (int64_t) maxImmedValue &&
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intValue >= -((int64_t) maxImmedValue+1))
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return true;
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}
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uint64_t maxImmedValue = maxImmedConstant(opCode, isSignExtended);
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if (maxImmedValue != 0) {
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// Now check if the constant fits
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if (intValue <= (int64_t) maxImmedValue &&
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intValue >= -((int64_t) maxImmedValue+1))
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return true;
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}
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return false;
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}
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//---------------------------------------------------------------------------
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// class MachineSchedInfo
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// Interface to machine description for instruction scheduling
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//---------------------------------------------------------------------------
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/*ctor*/
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MachineSchedInfo::MachineSchedInfo(int _numSchedClasses,
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const MachineInstrInfo* _mii,
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const InstrClassRUsage* _classRUsages,
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const InstrRUsageDelta* _usageDeltas,
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const InstrIssueDelta* _issueDeltas,
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unsigned int _numUsageDeltas,
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unsigned int _numIssueDeltas)
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: numSchedClasses(_numSchedClasses),
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mii(_mii),
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classRUsages(_classRUsages),
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usageDeltas(_usageDeltas),
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issueDeltas(_issueDeltas),
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numUsageDeltas(_numUsageDeltas),
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numIssueDeltas(_numIssueDeltas)
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{
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}
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void
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MachineSchedInfo::initializeResources()
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{
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assert(MAX_NUM_SLOTS >= (int) getMaxNumIssueTotal()
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&& "Insufficient slots for static data! Increase MAX_NUM_SLOTS");
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// First, compute common resource usage info for each class because
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// most instructions will probably behave the same as their class.
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// Cannot allocate a vector of InstrRUsage so new each one.
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//
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vector<InstrRUsage> instrRUForClasses;
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instrRUForClasses.resize(numSchedClasses);
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for (InstrSchedClass sc=0; sc < numSchedClasses; sc++)
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{
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// instrRUForClasses.push_back(new InstrRUsage);
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instrRUForClasses[sc].setMaxSlots(getMaxNumIssueTotal());
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instrRUForClasses[sc] = classRUsages[sc];
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}
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computeInstrResources(instrRUForClasses);
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computeIssueGaps(instrRUForClasses);
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}
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void
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MachineSchedInfo::computeInstrResources(const vector<InstrRUsage>& instrRUForClasses)
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{
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int numOpCodes = mii->getNumRealOpCodes();
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instrRUsages.resize(numOpCodes);
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// First get the resource usage information from the class resource usages.
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for (MachineOpCode op=0; op < numOpCodes; op++)
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{
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InstrSchedClass sc = getSchedClass(op);
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assert(sc >= 0 && sc < numSchedClasses);
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instrRUsages[op] = instrRUForClasses[sc];
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}
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// Now, modify the resource usages as specified in the deltas.
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for (unsigned i=0; i < numUsageDeltas; i++)
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{
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MachineOpCode op = usageDeltas[i].opCode;
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assert(op < numOpCodes);
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instrRUsages[op].addUsageDelta(usageDeltas[i]);
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}
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// Then modify the issue restrictions as specified in the deltas.
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for (unsigned i=0; i < numIssueDeltas; i++)
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{
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MachineOpCode op = issueDeltas[i].opCode;
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assert(op < numOpCodes);
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instrRUsages[issueDeltas[i].opCode].addIssueDelta(issueDeltas[i]);
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}
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}
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void
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MachineSchedInfo::computeIssueGaps(const vector<InstrRUsage>& instrRUForClasses)
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{
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int numOpCodes = mii->getNumRealOpCodes();
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instrRUsages.resize(numOpCodes);
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assert(numOpCodes < (1 << MAX_OPCODE_SIZE) - 1
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&& "numOpCodes invalid for implementation of class OpCodePair!");
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// First, compute issue gaps between pairs of classes based on common
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// resources usages for each class, because most instruction pairs will
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// usually behave the same as their class.
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//
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int classPairGaps[numSchedClasses][numSchedClasses];
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for (InstrSchedClass fromSC=0; fromSC < numSchedClasses; fromSC++)
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for (InstrSchedClass toSC=0; toSC < numSchedClasses; toSC++)
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{
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int classPairGap = ComputeMinGap(instrRUForClasses[fromSC],
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instrRUForClasses[toSC]);
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classPairGaps[fromSC][toSC] = classPairGap;
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}
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// Now, for each pair of instructions, use the class pair gap if both
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// instructions have identical resource usage as their respective classes.
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// If not, recompute the gap for the pair from scratch.
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longestIssueConflict = 0;
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for (MachineOpCode fromOp=0; fromOp < numOpCodes; fromOp++)
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for (MachineOpCode toOp=0; toOp < numOpCodes; toOp++)
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{
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int instrPairGap =
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(instrRUsages[fromOp].sameAsClass && instrRUsages[toOp].sameAsClass)
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? classPairGaps[getSchedClass(fromOp)][getSchedClass(toOp)]
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: ComputeMinGap(instrRUsages[fromOp], instrRUsages[toOp]);
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if (instrPairGap > 0)
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{
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issueGaps[OpCodePair(fromOp,toOp)] = instrPairGap;
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conflictLists[fromOp].push_back(toOp);
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longestIssueConflict = max(longestIssueConflict, instrPairGap);
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}
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}
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}
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// Check if fromRVec and toRVec have *any* common entries.
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// Assume the vectors are sorted in increasing order.
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// Algorithm copied from function set_intersection() for sorted ranges (stl_algo.h).
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inline static bool
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RUConflict(const vector<resourceId_t>& fromRVec,
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const vector<resourceId_t>& toRVec)
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{
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bool commonElementFound = false;
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unsigned fN = fromRVec.size(), tN = toRVec.size();
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unsigned fi = 0, ti = 0;
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while (fi < fN && ti < tN)
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if (fromRVec[fi] < toRVec[ti])
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++fi;
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else if (toRVec[ti] < fromRVec[fi])
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++ti;
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else
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{
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commonElementFound = true;
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break;
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}
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return commonElementFound;
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}
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static cycles_t
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ComputeMinGap(const InstrRUsage& fromRU, const InstrRUsage& toRU)
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{
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cycles_t minGap = 0;
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if (fromRU.numBubbles > 0)
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minGap = fromRU.numBubbles;
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if (minGap < fromRU.numCycles)
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{
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// only need to check from cycle `minGap' onwards
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for (cycles_t gap=minGap; gap <= fromRU.numCycles-1; gap++)
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{
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// check if instr. #2 can start executing `gap' cycles after #1
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// by checking for resource conflicts in each overlapping cycle
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cycles_t numOverlap = min(fromRU.numCycles - gap, toRU.numCycles);
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for (cycles_t c = 0; c <= numOverlap-1; c++)
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if (RUConflict(fromRU.resourcesByCycle[gap + c],
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toRU.resourcesByCycle[c]))
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{// conflict found so minGap must be more than `gap'
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minGap = gap+1;
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break;
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}
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}
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}
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return minGap;
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}
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//---------------------------------------------------------------------------
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