forked from OSchip/llvm-project
Completed basic intra block split implementation.
llvm-svn: 74114
This commit is contained in:
Lang Hames
parent
de018c412f
commit
6858b7d06a
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@ -78,24 +78,21 @@ protected:
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return miIdx;
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}
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/// Insert a store of the given vreg to the given stack slot immediately
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/// after the given instruction. Returns the base index of the inserted
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/// instruction. The caller is responsible for adding an appropriate
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/// LiveInterval to the LiveIntervals analysis.
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unsigned insertStoreFor(MachineInstr *mi, unsigned ss,
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unsigned insertStoreAfter(MachineInstr *mi, unsigned ss,
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unsigned vreg,
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const TargetRegisterClass *trc) {
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MachineBasicBlock::iterator nextInstItr(mi);
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++nextInstItr;
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MachineBasicBlock::iterator nextInstItr(next(mi));
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unsigned miIdx = makeSpaceAfter(mi);
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tii->storeRegToStackSlot(*mi->getParent(), nextInstItr, vreg,
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true, ss, trc);
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MachineBasicBlock::iterator storeInstItr(mi);
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++storeInstItr;
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MachineBasicBlock::iterator storeInstItr(next(mi));
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MachineInstr *storeInst = &*storeInstItr;
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unsigned storeInstIdx = miIdx + LiveInterval::InstrSlots::NUM;
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@ -107,37 +104,81 @@ protected:
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return storeInstIdx;
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}
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void insertStoreOnInterval(LiveInterval *li,
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MachineInstr *mi, unsigned ss,
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unsigned vreg,
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const TargetRegisterClass *trc) {
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/// Insert a store of the given vreg to the given stack slot immediately
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/// before the given instructnion. Returns the base index of the inserted
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/// Instruction.
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unsigned insertStoreBefore(MachineInstr *mi, unsigned ss,
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unsigned vreg,
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const TargetRegisterClass *trc) {
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unsigned miIdx = makeSpaceBefore(mi);
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tii->storeRegToStackSlot(*mi->getParent(), mi, vreg, true, ss, trc);
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MachineBasicBlock::iterator storeInstItr(prior(mi));
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MachineInstr *storeInst = &*storeInstItr;
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unsigned storeInstIdx = miIdx - LiveInterval::InstrSlots::NUM;
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unsigned storeInstIdx = insertStoreFor(mi, ss, vreg, trc);
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assert(lis->getInstructionFromIndex(storeInstIdx) == 0 &&
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"Store inst index already in use.");
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lis->InsertMachineInstrInMaps(storeInst, storeInstIdx);
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return storeInstIdx;
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}
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void insertStoreAfterInstOnInterval(LiveInterval *li,
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MachineInstr *mi, unsigned ss,
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unsigned vreg,
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const TargetRegisterClass *trc) {
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unsigned storeInstIdx = insertStoreAfter(mi, ss, vreg, trc);
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unsigned start = lis->getDefIndex(lis->getInstructionIndex(mi)),
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end = lis->getUseIndex(storeInstIdx);
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VNInfo *vni =
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li->getNextValue(storeInstIdx, 0, true, lis->getVNInfoAllocator());
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vni->kills.push_back(storeInstIdx);
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DOUT << " Inserting store range: [" << start << ", " << end << ")\n";
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LiveRange lr(start, end, vni);
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li->addRange(lr);
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}
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/// Insert a load of the given veg from the given stack slot immediately
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/// Insert a load of the given vreg from the given stack slot immediately
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/// after the given instruction. Returns the base index of the inserted
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/// instruction. The caller is responsibel for adding/removing an appropriate
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/// range vreg's LiveInterval.
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unsigned insertLoadAfter(MachineInstr *mi, unsigned ss,
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unsigned vreg,
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const TargetRegisterClass *trc) {
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MachineBasicBlock::iterator nextInstItr(next(mi));
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unsigned miIdx = makeSpaceAfter(mi);
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tii->loadRegFromStackSlot(*mi->getParent(), nextInstItr, vreg, ss, trc);
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MachineBasicBlock::iterator loadInstItr(next(mi));
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MachineInstr *loadInst = &*loadInstItr;
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unsigned loadInstIdx = miIdx + LiveInterval::InstrSlots::NUM;
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assert(lis->getInstructionFromIndex(loadInstIdx) == 0 &&
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"Store inst index already in use.");
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lis->InsertMachineInstrInMaps(loadInst, loadInstIdx);
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return loadInstIdx;
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}
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/// Insert a load of the given vreg from the given stack slot immediately
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/// before the given instruction. Returns the base index of the inserted
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/// instruction. The caller is responsible for adding an appropriate
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/// LiveInterval to the LiveIntervals analysis.
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unsigned insertLoadFor(MachineInstr *mi, unsigned ss,
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unsigned vreg,
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const TargetRegisterClass *trc) {
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MachineBasicBlock::iterator useInstItr(mi);
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unsigned insertLoadBefore(MachineInstr *mi, unsigned ss,
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unsigned vreg,
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const TargetRegisterClass *trc) {
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unsigned miIdx = makeSpaceBefore(mi);
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tii->loadRegFromStackSlot(*mi->getParent(), useInstItr, vreg, ss, trc);
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MachineBasicBlock::iterator loadInstItr(mi);
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--loadInstItr;
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tii->loadRegFromStackSlot(*mi->getParent(), mi, vreg, ss, trc);
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MachineBasicBlock::iterator loadInstItr(prior(mi));
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MachineInstr *loadInst = &*loadInstItr;
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unsigned loadInstIdx = miIdx - LiveInterval::InstrSlots::NUM;
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@ -149,18 +190,19 @@ protected:
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return loadInstIdx;
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}
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void insertLoadOnInterval(LiveInterval *li,
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MachineInstr *mi, unsigned ss,
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unsigned vreg,
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const TargetRegisterClass *trc) {
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void insertLoadBeforeInstOnInterval(LiveInterval *li,
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MachineInstr *mi, unsigned ss,
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unsigned vreg,
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const TargetRegisterClass *trc) {
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unsigned loadInstIdx = insertLoadFor(mi, ss, vreg, trc);
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unsigned loadInstIdx = insertLoadBefore(mi, ss, vreg, trc);
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unsigned start = lis->getDefIndex(loadInstIdx),
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end = lis->getUseIndex(lis->getInstructionIndex(mi));
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VNInfo *vni =
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li->getNextValue(loadInstIdx, 0, true, lis->getVNInfoAllocator());
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vni->kills.push_back(lis->getInstructionIndex(mi));
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DOUT << " Intserting load range: [" << start << ", " << end << ")\n";
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LiveRange lr(start, end, vni);
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li->addRange(lr);
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@ -180,6 +222,8 @@ protected:
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assert(!li->isStackSlot() &&
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"Trying to spill a stack slot.");
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DOUT << "Trivial spill everywhere of reg" << li->reg << "\n";
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std::vector<LiveInterval*> added;
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const TargetRegisterClass *trc = mri->getRegClass(li->reg);
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@ -189,6 +233,9 @@ protected:
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regItr = mri->reg_begin(li->reg); regItr != mri->reg_end();) {
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MachineInstr *mi = &*regItr;
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DOUT << " Processing " << *mi;
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do {
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++regItr;
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} while (regItr != mri->reg_end() && (&*regItr == mi));
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@ -227,11 +274,11 @@ protected:
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assert(hasUse || hasDef);
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if (hasUse) {
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insertLoadOnInterval(newLI, mi, ss, newVReg, trc);
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insertLoadBeforeInstOnInterval(newLI, mi, ss, newVReg, trc);
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}
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if (hasDef) {
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insertStoreOnInterval(newLI, mi, ss, newVReg, trc);
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insertStoreAfterInstOnInterval(newLI, mi, ss, newVReg, trc);
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}
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added.push_back(newLI);
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@ -258,29 +305,53 @@ public:
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std::vector<LiveInterval*> intraBlockSplit(LiveInterval *li, VNInfo *valno) {
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std::vector<LiveInterval*> spillIntervals;
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MachineBasicBlock::iterator storeInsertPoint;
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if (!valno->isDefAccurate() && !valno->isPHIDef()) {
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// Early out for values which have no well defined def point.
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return spillIntervals;
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}
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// Ok.. we should be able to proceed...
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const TargetRegisterClass *trc = mri->getRegClass(li->reg);
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unsigned ss = vrm->assignVirt2StackSlot(li->reg);
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vrm->grow();
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vrm->assignVirt2StackSlot(li->reg, ss);
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MachineInstr *mi = 0;
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unsigned storeIdx = 0;
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if (valno->isDefAccurate()) {
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// If we have an accurate def we can just grab an iterator to the instr
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// after the def.
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storeInsertPoint =
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next(MachineBasicBlock::iterator(lis->getInstructionFromIndex(valno->def)));
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mi = lis->getInstructionFromIndex(valno->def);
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storeIdx = insertStoreAfter(mi, ss, li->reg, trc) +
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LiveInterval::InstrSlots::DEF;
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} else {
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// If the def info isn't accurate we check if this is a PHI def.
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// If it is then def holds the index of the defining Basic Block, and we
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// can use that to get an insertion point.
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if (valno->isPHIDef()) {
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} else {
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// We have no usable def info. We can't split this value sensibly.
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// FIXME: Need sensible feedback for "failure to split", an empty
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// set of spill intervals could be reasonably returned from a
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// split where both the store and load are folded.
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return spillIntervals;
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}
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// if we get here we have a PHI def.
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mi = &lis->getMBBFromIndex(valno->def)->front();
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storeIdx = insertStoreBefore(mi, ss, li->reg, trc) +
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LiveInterval::InstrSlots::DEF;
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}
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MachineBasicBlock *defBlock = mi->getParent();
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unsigned loadIdx = 0;
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// Now we need to find the load...
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MachineBasicBlock::iterator useItr(mi);
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for (; !useItr->readsRegister(li->reg); ++useItr) {}
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if (useItr != defBlock->end()) {
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MachineInstr *loadInst = useItr;
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loadIdx = insertLoadBefore(loadInst, ss, li->reg, trc) +
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LiveInterval::InstrSlots::USE;
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}
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else {
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MachineInstr *loadInst = &defBlock->back();
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loadIdx = insertLoadAfter(loadInst, ss, li->reg, trc) +
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LiveInterval::InstrSlots::USE;
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}
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li->removeRange(storeIdx, loadIdx, true);
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return spillIntervals;
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}
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