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[IR] Add NoUndef attribute to Intrinsics.td 

This patch adds NoUndef to Intrinsics.td.
The attribute is attached to llvm.assume's operand, because llvm.assume(undef)
is UB.
It is attached to pointer operands of several memory accessing intrinsics
as well.

This change makes ValueTracking::getGuaranteedNonPoisonOps' intrinsic check
unnecessary, so it is removed.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D86576
This commit is contained in:
Juneyoung Lee 2020-08-26 04:50:29 +09:00
parent 09288bcbf5
commit 684b43c0cf
7 changed files with 29 additions and 19 deletions
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18
llvm/include/llvm/IR/Intrinsics.td
View File

@ -83,6 +83,11 @@ class NoAlias<AttrIndex idx> : IntrinsicProperty {
int ArgNo = idx.Value;
}
// NoUndef - The specified argument is neither undef nor poison.
class NoUndef<AttrIndex idx> : IntrinsicProperty {
int ArgNo = idx.Value;
}
class Align<AttrIndex idx, int align> : IntrinsicProperty {
int ArgNo = idx.Value;
int Align = align;
@ -515,7 +520,8 @@ def int_readcyclecounter : Intrinsic<[llvm_i64_ty]>;
// The assume intrinsic is marked as arbitrarily writing so that proper
// control dependencies will be maintained.
def int_assume : Intrinsic<[], [llvm_i1_ty], [IntrWillReturn]>;
def int_assume : Intrinsic<[], [llvm_i1_ty], [IntrWillReturn,
NoUndef<ArgIndex<0>>]>;
// Stack Protector Intrinsic - The stackprotector intrinsic writes the stack
// guard to the correct place on the stack frame.
@ -1347,26 +1353,28 @@ def int_masked_store : Intrinsic<[], [llvm_anyvector_ty,
LLVMAnyPointerType<LLVMMatchType<0>>,
llvm_i32_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
[IntrArgMemOnly, IntrWillReturn, ImmArg<ArgIndex<2>>]>;
[IntrArgMemOnly, IntrWillReturn,
NoUndef<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
def int_masked_load : Intrinsic<[llvm_anyvector_ty],
[LLVMAnyPointerType<LLVMMatchType<0>>, llvm_i32_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<0>],
[IntrReadMem, IntrArgMemOnly, IntrWillReturn,
ImmArg<ArgIndex<1>>]>;
NoUndef<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
def int_masked_gather: Intrinsic<[llvm_anyvector_ty],
[LLVMVectorOfAnyPointersToElt<0>, llvm_i32_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
LLVMMatchType<0>],
[IntrReadMem, IntrWillReturn,
ImmArg<ArgIndex<1>>]>;
NoUndef<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
def int_masked_scatter: Intrinsic<[],
[llvm_anyvector_ty,
LLVMVectorOfAnyPointersToElt<0>, llvm_i32_ty,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>],
[IntrWillReturn, ImmArg<ArgIndex<2>>]>;
[IntrWillReturn, NoUndef<ArgIndex<1>>,
ImmArg<ArgIndex<2>>]>;
def int_masked_expandload: Intrinsic<[llvm_anyvector_ty],
[LLVMPointerToElt<0>,

10
llvm/lib/Analysis/ValueTracking.cpp
View File

@ -5093,16 +5093,6 @@ void llvm::getGuaranteedNonPoisonOps(const Instruction *I,
case Instruction::Call:
case Instruction::Invoke: {
if (auto *II = dyn_cast<IntrinsicInst>(I)) {
switch (II->getIntrinsicID()) {
case Intrinsic::assume:
Operands.insert(II->getArgOperand(0));
break;
default:
break;
}
}
const CallBase *CB = cast<CallBase>(I);
if (CB->isIndirectCall())
Operands.insert(CB->getCalledOperand());

2
llvm/test/Transforms/EarlyCSE/invariant.start.ll
View File

@ -525,3 +525,5 @@ define i32 @test_invariant_load_scope(i32* %p) {
%sub = sub i32 %v1, %v2
ret i32 %sub
}
; USE_ASSUME: declare void @llvm.assume(i1 noundef)

1
llvm/utils/TableGen/CodeGenIntrinsics.h
View File

@ -148,6 +148,7 @@ struct CodeGenIntrinsic {
enum ArgAttrKind {
NoCapture,
NoAlias,
NoUndef,
Returned,
ReadOnly,
WriteOnly,

3
llvm/utils/TableGen/CodeGenTarget.cpp
View File

@ -846,6 +846,9 @@ void CodeGenIntrinsic::setProperty(Record *R) {
} else if (R->isSubClassOf("NoAlias")) {
unsigned ArgNo = R->getValueAsInt("ArgNo");
ArgumentAttributes.emplace_back(ArgNo, NoAlias, 0);
} else if (R->isSubClassOf("NoUndef")) {
unsigned ArgNo = R->getValueAsInt("ArgNo");
ArgumentAttributes.emplace_back(ArgNo, NoUndef, 0);
} else if (R->isSubClassOf("Returned")) {
unsigned ArgNo = R->getValueAsInt("ArgNo");
ArgumentAttributes.emplace_back(ArgNo, Returned, 0);

6
llvm/utils/TableGen/IntrinsicEmitter.cpp
View File

@ -687,6 +687,12 @@ void IntrinsicEmitter::EmitAttributes(const CodeGenIntrinsicTable &Ints,
OS << "Attribute::NoAlias";
addComma = true;
break;
case CodeGenIntrinsic::NoUndef:
if (addComma)
OS << ",";
OS << "Attribute::NoUndef";
addComma = true;
break;
case CodeGenIntrinsic::Returned:
if (addComma)
OS << ",";

8
mlir/test/Target/llvmir-intrinsics.mlir
View File

@ -322,10 +322,10 @@ llvm.func @memcpy_test(%arg0: !llvm.i32, %arg1: !llvm.i1, %arg2: !llvm.ptr<i8>,
// CHECK-DAG: declare <48 x float> @llvm.matrix.column.major.load.v48f32(float* nocapture, i64, i1 immarg, i32 immarg, i32 immarg)
// CHECK-DAG: declare void @llvm.matrix.column.major.store.v48f32(<48 x float>, float* nocapture writeonly, i64, i1 immarg, i32 immarg, i32 immarg)
// CHECK-DAG: declare <7 x i1> @llvm.get.active.lane.mask.v7i1.i64(i64, i64)
// CHECK-DAG: declare <7 x float> @llvm.masked.load.v7f32.p0v7f32(<7 x float>*, i32 immarg, <7 x i1>, <7 x float>)
// CHECK-DAG: declare void @llvm.masked.store.v7f32.p0v7f32(<7 x float>, <7 x float>*, i32 immarg, <7 x i1>)
// CHECK-DAG: declare <7 x float> @llvm.masked.gather.v7f32.v7p0f32(<7 x float*>, i32 immarg, <7 x i1>, <7 x float>)
// CHECK-DAG: declare void @llvm.masked.scatter.v7f32.v7p0f32(<7 x float>, <7 x float*>, i32 immarg, <7 x i1>)
// CHECK-DAG: declare <7 x float> @llvm.masked.load.v7f32.p0v7f32(<7 x float>* noundef, i32 immarg, <7 x i1>, <7 x float>)
// CHECK-DAG: declare void @llvm.masked.store.v7f32.p0v7f32(<7 x float>, <7 x float>* noundef, i32 immarg, <7 x i1>)
// CHECK-DAG: declare <7 x float> @llvm.masked.gather.v7f32.v7p0f32(<7 x float*> noundef, i32 immarg, <7 x i1>, <7 x float>)
// CHECK-DAG: declare void @llvm.masked.scatter.v7f32.v7p0f32(<7 x float>, <7 x float*> noundef, i32 immarg, <7 x i1>)
// CHECK-DAG: declare <7 x float> @llvm.masked.expandload.v7f32(float*, <7 x i1>, <7 x float>)
// CHECK-DAG: declare void @llvm.masked.compressstore.v7f32(<7 x float>, float*, <7 x i1>)
// CHECK-DAG: declare void @llvm.memcpy.p0i8.p0i8.i32(i8* noalias nocapture writeonly, i8* noalias nocapture readonly, i32, i1 immarg)