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[X86] Create schedule classes for BT(C|R|S)mi and BT(C|R|S)mr instructions 

llvm-svn: 343490
This commit is contained in:
Simon Pilgrim 2018-10-01 16:12:44 +00:00
parent 55b9a5395b
commit 683e35527b
11 changed files with 71 additions and 49 deletions
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12
llvm/lib/Target/X86/X86InstrInfo.td
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@ -1830,7 +1830,7 @@ def BTC64rr : RI<0xBB, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2
NotMemoryFoldable;
} // SchedRW
let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetRegRMW] in {
def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
"btc{w}\t{$src2, $src1|$src1, $src2}", []>,
OpSize16, TB, NotMemoryFoldable;
@ -1851,7 +1851,7 @@ def BTC64ri8 : RIi8<0xBA, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$sr
"btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
} // SchedRW
let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetImmRMW] in {
def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
"btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB;
def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
@ -1873,7 +1873,7 @@ def BTR64rr : RI<0xB3, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2
NotMemoryFoldable;
} // SchedRW
let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetRegRMW] in {
def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
"btr{w}\t{$src2, $src1|$src1, $src2}", []>,
OpSize16, TB, NotMemoryFoldable;
@ -1896,7 +1896,7 @@ def BTR64ri8 : RIi8<0xBA, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$sr
"btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
} // SchedRW
let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetImmRMW] in {
def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
"btr{w}\t{$src2, $src1|$src1, $src2}", []>,
OpSize16, TB;
@ -1920,7 +1920,7 @@ def BTS64rr : RI<0xAB, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2
NotMemoryFoldable;
} // SchedRW
let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetRegRMW] in {
def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
"bts{w}\t{$src2, $src1|$src1, $src2}", []>,
OpSize16, TB, NotMemoryFoldable;
@ -1941,7 +1941,7 @@ def BTS64ri8 : RIi8<0xBA, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$sr
"bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
} // SchedRW
let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetImmRMW] in {
def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
"bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB;
def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),

12
llvm/lib/Target/X86/X86SchedBroadwell.td
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@ -162,11 +162,13 @@ def : WriteRes<WriteSETCCStore, [BWPort06,BWPort4,BWPort237]> {
let NumMicroOps = 3;
}
defm : X86WriteRes<WriteLAHFSAHF, [BWPort06], 1, [1], 1>;
defm : X86WriteRes<WriteBitTest, [BWPort06], 1, [1], 1>; // Bit Test instrs
defm : X86WriteRes<WriteBitTestImmLd, [BWPort06,BWPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestRegLd, [BWPort0156,BWPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestSet, [BWPort06], 1, [1], 1>; // Bit Test + Set instrs
defm : X86WriteRes<WriteLAHFSAHF, [BWPort06], 1, [1], 1>;
defm : X86WriteRes<WriteBitTest, [BWPort06], 1, [1], 1>; // Bit Test instrs
defm : X86WriteRes<WriteBitTestImmLd, [BWPort06,BWPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestRegLd, [BWPort0156,BWPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestSet, [BWPort06], 1, [1], 1>; // Bit Test + Set instrs
defm : X86WriteRes<WriteBitTestSetImmLd, [BWPort06,BWPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestSetRegLd, [BWPort0156,BWPort23], 5, [1,1], 2>;
// Bit counts.
defm : BWWriteResPair<WriteBSF, [BWPort1], 3>;

12
llvm/lib/Target/X86/X86SchedHaswell.td
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@ -166,11 +166,13 @@ def : WriteRes<WriteSETCCStore, [HWPort06,HWPort4,HWPort237]> {
let NumMicroOps = 3;
}
defm : X86WriteRes<WriteLAHFSAHF, [HWPort06], 1, [1], 1>;
defm : X86WriteRes<WriteBitTest, [HWPort06], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestImmLd, [HWPort06,HWPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestRegLd, [], 1, [], 10>;
defm : X86WriteRes<WriteBitTestSet, [HWPort06], 1, [1], 1>;
defm : X86WriteRes<WriteLAHFSAHF, [HWPort06], 1, [1], 1>;
defm : X86WriteRes<WriteBitTest, [HWPort06], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestImmLd, [HWPort06,HWPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestRegLd, [], 1, [], 10>;
defm : X86WriteRes<WriteBitTestSet, [HWPort06], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestSetImmLd, [HWPort06,HWPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestSetRegLd, [], 1, [], 11>;
// This is for simple LEAs with one or two input operands.
// The complex ones can only execute on port 1, and they require two cycles on

12
llvm/lib/Target/X86/X86SchedSandyBridge.td
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@ -161,11 +161,13 @@ def : WriteRes<WriteSETCCStore, [SBPort05,SBPort4,SBPort23]> {
let NumMicroOps = 3;
}
defm : X86WriteRes<WriteLAHFSAHF, [SBPort05], 1, [1], 1>;
defm : X86WriteRes<WriteBitTest, [SBPort05], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestImmLd, [SBPort05,SBPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestRegLd, [SBPort05,SBPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestSet, [SBPort05], 1, [1], 1>;
defm : X86WriteRes<WriteLAHFSAHF, [SBPort05], 1, [1], 1>;
defm : X86WriteRes<WriteBitTest, [SBPort05], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestImmLd, [SBPort05,SBPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestRegLd, [SBPort05,SBPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestSet, [SBPort05], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestSetImmLd, [SBPort05,SBPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestSetRegLd, [SBPort05,SBPort23], 6, [1,1], 2>;
// This is for simple LEAs with one or two input operands.
// The complex ones can only execute on port 1, and they require two cycles on

12
llvm/lib/Target/X86/X86SchedSkylakeClient.td
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@ -159,11 +159,13 @@ def : WriteRes<WriteSETCCStore, [SKLPort06,SKLPort4,SKLPort237]> {
let NumMicroOps = 3;
}
defm : X86WriteRes<WriteLAHFSAHF, [SKLPort06], 1, [1], 1>;
defm : X86WriteRes<WriteBitTest, [SKLPort06], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestImmLd, [SKLPort06,SKLPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestRegLd, [SKLPort0156,SKLPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestSet, [SKLPort06], 1, [1], 1>;
defm : X86WriteRes<WriteLAHFSAHF, [SKLPort06], 1, [1], 1>;
defm : X86WriteRes<WriteBitTest, [SKLPort06], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestImmLd, [SKLPort06,SKLPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestRegLd, [SKLPort0156,SKLPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestSet, [SKLPort06], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestSetImmLd, [SKLPort06,SKLPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestSetRegLd, [SKLPort0156,SKLPort23], 5, [1,1], 2>;
// Bit counts.
defm : SKLWriteResPair<WriteBSF, [SKLPort1], 3>;

12
llvm/lib/Target/X86/X86SchedSkylakeServer.td
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@ -159,11 +159,13 @@ def : WriteRes<WriteSETCCStore, [SKXPort06,SKXPort4,SKXPort237]> {
let Latency = 2;
let NumMicroOps = 3;
}
defm : X86WriteRes<WriteLAHFSAHF, [SKXPort06], 1, [1], 1>;
defm : X86WriteRes<WriteBitTest, [SKXPort06], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestImmLd, [SKXPort06,SKXPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestRegLd, [SKXPort0156,SKXPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestSet, [SKXPort06], 1, [1], 1>;
defm : X86WriteRes<WriteLAHFSAHF, [SKXPort06], 1, [1], 1>;
defm : X86WriteRes<WriteBitTest, [SKXPort06], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestImmLd, [SKXPort06,SKXPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestRegLd, [SKXPort0156,SKXPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestSet, [SKXPort06], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestSetImmLd, [SKXPort06,SKXPort23], 6, [1,1], 2>;
defm : X86WriteRes<WriteBitTestSetRegLd, [SKXPort0156,SKXPort23], 5, [1,1], 2>;
// Integer shifts and rotates.
defm : SKXWriteResPair<WriteShift, [SKXPort06], 1>;

6
llvm/lib/Target/X86/X86Schedule.td
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@ -160,7 +160,11 @@ def WriteBitTest : SchedWrite; // Bit Test
def WriteBitTestImmLd : SchedWrite;
def WriteBitTestRegLd : SchedWrite;
def WriteBitTestSet : SchedWrite; // Bit Test + Set - TODO add memory folding support
def WriteBitTestSet : SchedWrite; // Bit Test + Set
def WriteBitTestSetImmLd : SchedWrite;
def WriteBitTestSetRegLd : SchedWrite;
def WriteBitTestSetImmRMW : WriteSequence<[WriteBitTestSetImmLd, WriteRMW]>;
def WriteBitTestSetRegRMW : WriteSequence<[WriteBitTestSetRegLd, WriteRMW]>;
// Integer shifts and rotates.
defm WriteShift : X86SchedWritePair;

10
llvm/lib/Target/X86/X86ScheduleAtom.td
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@ -121,10 +121,12 @@ def : WriteRes<WriteLAHFSAHF, [AtomPort01]> {
let Latency = 2;
let ResourceCycles = [2];
}
defm : X86WriteRes<WriteBitTest, [AtomPort1], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestImmLd, [AtomPort0], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestRegLd, [AtomPort01], 9, [9], 1>;
defm : X86WriteRes<WriteBitTestSet, [AtomPort1], 1, [1], 1>;
defm : X86WriteRes<WriteBitTest, [AtomPort1], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestImmLd, [AtomPort0], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestRegLd, [AtomPort01], 9, [9], 1>;
defm : X86WriteRes<WriteBitTestSet, [AtomPort1], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestSetImmLd, [AtomPort1], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestSetRegLd, [AtomPort1], 1, [1], 1>;
// This is for simple LEAs with one or two input operands.
def : WriteRes<WriteLEA, [AtomPort1]>;

10
llvm/lib/Target/X86/X86ScheduleBtVer2.td
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@ -204,10 +204,12 @@ def : WriteRes<WriteSETCC, [JALU01]>; // Setcc.
def : WriteRes<WriteSETCCStore, [JALU01,JSAGU]>;
def : WriteRes<WriteLAHFSAHF, [JALU01]>;
defm : X86WriteRes<WriteBitTest, [JALU01], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestImmLd, [JALU01, JLAGU], 4, [1, 1], 1>;
defm : X86WriteRes<WriteBitTestRegLd, [JALU01, JLAGU], 4, [1, 1], 5>;
defm : X86WriteRes<WriteBitTestSet, [JALU01], 1, [1], 2>;
defm : X86WriteRes<WriteBitTest, [JALU01], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestImmLd, [JALU01,JLAGU], 4, [1,1], 1>;
defm : X86WriteRes<WriteBitTestRegLd, [JALU01,JLAGU], 4, [1,1], 5>;
defm : X86WriteRes<WriteBitTestSet, [JALU01], 1, [1], 2>;
defm : X86WriteRes<WriteBitTestSetImmLd, [JALU01,JLAGU], 3, [1,1], 1>;
defm : X86WriteRes<WriteBitTestSetRegLd, [JALU01,JLAGU], 3, [1,1], 1>;
// This is for simple LEAs with one or two input operands.
def : WriteRes<WriteLEA, [JALU01]>;

12
llvm/lib/Target/X86/X86ScheduleSLM.td
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@ -134,11 +134,13 @@ def : WriteRes<WriteSETCCStore, [SLM_IEC_RSV01, SLM_MEC_RSV]> {
// FIXME Latency and NumMicrOps?
let ResourceCycles = [2,1];
}
defm : X86WriteRes<WriteLAHFSAHF, [SLM_IEC_RSV01], 1, [1], 1>;
defm : X86WriteRes<WriteBitTest, [SLM_IEC_RSV01], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestImmLd, [SLM_IEC_RSV01, SLM_MEC_RSV], 4, [1,1], 1>;
defm : X86WriteRes<WriteBitTestRegLd, [SLM_IEC_RSV01, SLM_MEC_RSV], 4, [1,1], 1>;
defm : X86WriteRes<WriteBitTestSet, [SLM_IEC_RSV01], 1, [1], 1>;
defm : X86WriteRes<WriteLAHFSAHF, [SLM_IEC_RSV01], 1, [1], 1>;
defm : X86WriteRes<WriteBitTest, [SLM_IEC_RSV01], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestImmLd, [SLM_IEC_RSV01, SLM_MEC_RSV], 4, [1,1], 1>;
defm : X86WriteRes<WriteBitTestRegLd, [SLM_IEC_RSV01, SLM_MEC_RSV], 4, [1,1], 1>;
defm : X86WriteRes<WriteBitTestSet, [SLM_IEC_RSV01], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestSetImmLd, [SLM_IEC_RSV01, SLM_MEC_RSV], 3, [1,1], 1>;
defm : X86WriteRes<WriteBitTestSetRegLd, [SLM_IEC_RSV01, SLM_MEC_RSV], 3, [1,1], 1>;
// This is for simple LEAs with one or two input operands.
// The complex ones can only execute on port 1, and they require two cycles on

10
llvm/lib/Target/X86/X86ScheduleZnver1.td
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@ -214,10 +214,12 @@ def : WriteRes<WriteSETCC, [ZnALU]>;
def : WriteRes<WriteSETCCStore, [ZnALU, ZnAGU]>;
defm : X86WriteRes<WriteLAHFSAHF, [ZnALU], 2, [1], 2>;
defm : X86WriteRes<WriteBitTest, [ZnALU], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestImmLd, [ZnALU,ZnAGU], 5, [1,1], 2>;
defm : X86WriteRes<WriteBitTestRegLd, [ZnALU,ZnAGU], 5, [1,1], 2>;
defm : X86WriteRes<WriteBitTestSet, [ZnALU], 2, [1], 2>;
defm : X86WriteRes<WriteBitTest, [ZnALU], 1, [1], 1>;
defm : X86WriteRes<WriteBitTestImmLd, [ZnALU,ZnAGU], 5, [1,1], 2>;
defm : X86WriteRes<WriteBitTestRegLd, [ZnALU,ZnAGU], 5, [1,1], 2>;
defm : X86WriteRes<WriteBitTestSet, [ZnALU], 2, [1], 2>;
defm : X86WriteRes<WriteBitTestSetImmLd, [ZnALU,ZnAGU], 5, [1,1], 2>;
defm : X86WriteRes<WriteBitTestSetRegLd, [ZnALU,ZnAGU], 5, [1,1], 2>;
// Bit counts.
defm : ZnWriteResPair<WriteBSF, [ZnALU], 3>;