forked from OSchip/llvm-project
[X86] Add missing memory variants to AVX false dependency breaking
Adds missing memory instruction variants to AVX false dependency breaking handling. (SSE was handled in r224246) Differential Revision: http://reviews.llvm.org/D6780 llvm-svn: 224900
This commit is contained in:
Michael Kuperstein
parent
22ee3f63b9
commit
683c3cde43
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@ -4554,28 +4554,52 @@ getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
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static bool hasUndefRegUpdate(unsigned Opcode) {
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switch (Opcode) {
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case X86::VCVTSI2SSrr:
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case X86::VCVTSI2SSrm:
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case X86::Int_VCVTSI2SSrr:
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case X86::Int_VCVTSI2SSrm:
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case X86::VCVTSI2SS64rr:
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case X86::VCVTSI2SS64rm:
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case X86::Int_VCVTSI2SS64rr:
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case X86::Int_VCVTSI2SS64rm:
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case X86::VCVTSI2SDrr:
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case X86::VCVTSI2SDrm:
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case X86::Int_VCVTSI2SDrr:
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case X86::Int_VCVTSI2SDrm:
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case X86::VCVTSI2SD64rr:
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case X86::VCVTSI2SD64rm:
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case X86::Int_VCVTSI2SD64rr:
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case X86::Int_VCVTSI2SD64rm:
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case X86::VCVTSD2SSrr:
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case X86::VCVTSD2SSrm:
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case X86::Int_VCVTSD2SSrr:
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case X86::Int_VCVTSD2SSrm:
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case X86::VCVTSS2SDrr:
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case X86::VCVTSS2SDrm:
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case X86::Int_VCVTSS2SDrr:
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case X86::Int_VCVTSS2SDrm:
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case X86::VRCPSSr:
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case X86::VRCPSSm:
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case X86::VRCPSSm_Int:
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case X86::VROUNDSDr:
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case X86::VROUNDSDm:
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case X86::VROUNDSDr_Int:
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case X86::VROUNDSSr:
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case X86::VROUNDSSm:
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case X86::VROUNDSSr_Int:
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case X86::VRSQRTSSr:
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case X86::VRSQRTSSm:
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case X86::VRSQRTSSm_Int:
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case X86::VSQRTSSr:
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// AVX-512
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case X86::VSQRTSSm:
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case X86::VSQRTSSm_Int:
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case X86::VSQRTSDr:
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case X86::VSQRTSDm:
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case X86::VSQRTSDm_Int:
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// AVX-512
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case X86::VCVTSD2SSZrr:
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case X86::VCVTSD2SSZrm:
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case X86::VCVTSS2SDZrr:
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case X86::VCVTSS2SDZrm:
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return true;
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}
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@ -1,29 +0,0 @@
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; RUN: llc < %s -march=x86-64 -mattr=+avx | FileCheck %s
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;
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; rdar:15221834 False AVX register dependencies cause 5x slowdown on
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; flops-6. Make sure the unused register read by vcvtsi2sdq is zeroed
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; to avoid cyclic dependence on a write to the same register in a
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; previous iteration.
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; CHECK-LABEL: t1:
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; CHECK-LABEL: %loop
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; CHECK: vxorps %[[REG:xmm.]], %{{xmm.}}, %{{xmm.}}
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; CHECK: vcvtsi2sdq %{{r[0-9a-x]+}}, %[[REG]], %{{xmm.}}
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define i64 @t1(i64* nocapture %x, double* nocapture %y) nounwind {
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entry:
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%vx = load i64* %x
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br label %loop
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loop:
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%i = phi i64 [ 1, %entry ], [ %inc, %loop ]
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%s1 = phi i64 [ %vx, %entry ], [ %s2, %loop ]
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%fi = sitofp i64 %i to double
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%vy = load double* %y
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%fipy = fadd double %fi, %vy
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%iipy = fptosi double %fipy to i64
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%s2 = add i64 %s1, %iipy
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%inc = add nsw i64 %i, 1
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%exitcond = icmp eq i64 %inc, 156250000
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br i1 %exitcond, label %ret, label %loop
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ret:
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ret i64 %s2
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}
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@ -1,11 +1,12 @@
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; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse2 -mcpu=nehalem | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse2 -mcpu=nehalem | FileCheck %s
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; RUN: llc < %s -mtriple=x86_64-linux -mattr=+sse2 -mcpu=nehalem | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse2 -mcpu=nehalem | FileCheck %s --check-prefix=SSE
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; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+avx -mcpu=corei7-avx | FileCheck %s --check-prefix=AVX
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define double @t1(float* nocapture %x) nounwind readonly ssp {
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entry:
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; CHECK-LABEL: t1:
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; CHECK: movss ([[A0:%rdi|%rcx]]), %xmm0
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; CHECK: cvtss2sd %xmm0, %xmm0
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; SSE-LABEL: t1:
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; SSE: movss ([[A0:%rdi|%rcx]]), %xmm0
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; SSE: cvtss2sd %xmm0, %xmm0
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%0 = load float* %x, align 4
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%1 = fpext float %0 to double
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@ -14,8 +15,8 @@ entry:
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define float @t2(double* nocapture %x) nounwind readonly ssp optsize {
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entry:
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; CHECK-LABEL: t2:
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; CHECK: cvtsd2ss ([[A0]]), %xmm0
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; SSE-LABEL: t2:
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; SSE: cvtsd2ss ([[A0]]), %xmm0
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%0 = load double* %x, align 8
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%1 = fptrunc double %0 to float
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ret float %1
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@ -23,9 +24,9 @@ entry:
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define float @squirtf(float* %x) nounwind {
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entry:
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; CHECK-LABEL: squirtf:
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; CHECK: movss ([[A0]]), %xmm0
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; CHECK: sqrtss %xmm0, %xmm0
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; SSE-LABEL: squirtf:
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; SSE: movss ([[A0]]), %xmm0
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; SSE: sqrtss %xmm0, %xmm0
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%z = load float* %x
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%t = call float @llvm.sqrt.f32(float %z)
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ret float %t
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@ -33,9 +34,9 @@ entry:
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define double @squirt(double* %x) nounwind {
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entry:
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; CHECK-LABEL: squirt:
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; CHECK: movsd ([[A0]]), %xmm0
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; CHECK: sqrtsd %xmm0, %xmm0
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; SSE-LABEL: squirt:
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; SSE: movsd ([[A0]]), %xmm0
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; SSE: sqrtsd %xmm0, %xmm0
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%z = load double* %x
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%t = call double @llvm.sqrt.f64(double %z)
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ret double %t
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@ -43,8 +44,8 @@ entry:
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define float @squirtf_size(float* %x) nounwind optsize {
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entry:
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; CHECK-LABEL: squirtf_size:
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; CHECK: sqrtss ([[A0]]), %xmm0
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; SSE-LABEL: squirtf_size:
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; SSE: sqrtss ([[A0]]), %xmm0
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%z = load float* %x
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%t = call float @llvm.sqrt.f32(float %z)
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ret float %t
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@ -52,8 +53,8 @@ entry:
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define double @squirt_size(double* %x) nounwind optsize {
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entry:
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; CHECK-LABEL: squirt_size:
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; CHECK: sqrtsd ([[A0]]), %xmm0
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; SSE-LABEL: squirt_size:
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; SSE: sqrtsd ([[A0]]), %xmm0
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%z = load double* %x
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%t = call double @llvm.sqrt.f64(double %z)
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ret double %t
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@ -62,8 +63,8 @@ entry:
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declare float @llvm.sqrt.f32(float)
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declare double @llvm.sqrt.f64(double)
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; CHECK-LABEL: loopdep1
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; CHECK: for.body
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; SSE-LABEL: loopdep1
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; SSE: for.body
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;
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; This loop contains two cvtsi2ss instructions that update the same xmm
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; register. Verify that the execution dependency fix pass breaks those
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@ -71,12 +72,12 @@ declare double @llvm.sqrt.f64(double)
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;
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; If the register allocator chooses different registers for the two cvtsi2ss
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; instructions, they are still dependent on themselves.
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; CHECK: xorps [[XMM1:%xmm[0-9]+]]
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; CHECK: , [[XMM1]]
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; CHECK: cvtsi2ssl %{{.*}}, [[XMM1]]
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; CHECK: xorps [[XMM2:%xmm[0-9]+]]
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; CHECK: , [[XMM2]]
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; CHECK: cvtsi2ssl %{{.*}}, [[XMM2]]
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; SSE: xorps [[XMM1:%xmm[0-9]+]]
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; SSE: , [[XMM1]]
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; SSE: cvtsi2ssl %{{.*}}, [[XMM1]]
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; SSE: xorps [[XMM2:%xmm[0-9]+]]
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; SSE: , [[XMM2]]
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; SSE: cvtsi2ssl %{{.*}}, [[XMM2]]
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;
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define float @loopdep1(i32 %m) nounwind uwtable readnone ssp {
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entry:
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@ -104,6 +105,38 @@ for.end: ; preds = %for.body, %entry
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ret float %sub
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}
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; rdar:15221834 False AVX register dependencies cause 5x slowdown on
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; flops-6. Make sure the unused register read by vcvtsi2sdq is zeroed
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; to avoid cyclic dependence on a write to the same register in a
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; previous iteration.
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; AVX-LABEL: loopdep2:
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; AVX-LABEL: %loop
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; AVX: vxorps %[[REG:xmm.]], %{{xmm.}}, %{{xmm.}}
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; AVX: vcvtsi2sdq %{{r[0-9a-x]+}}, %[[REG]], %{{xmm.}}
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; SSE-LABEL: loopdep2:
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; SSE-LABEL: %loop
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; SSE: xorps %[[REG:xmm.]], %[[REG]]
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; SSE: cvtsi2sdq %{{r[0-9a-x]+}}, %[[REG]]
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define i64 @loopdep2(i64* nocapture %x, double* nocapture %y) nounwind {
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entry:
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%vx = load i64* %x
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br label %loop
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loop:
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%i = phi i64 [ 1, %entry ], [ %inc, %loop ]
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%s1 = phi i64 [ %vx, %entry ], [ %s2, %loop ]
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%fi = sitofp i64 %i to double
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%vy = load double* %y
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%fipy = fadd double %fi, %vy
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%iipy = fptosi double %fipy to i64
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%s2 = add i64 %s1, %iipy
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%inc = add nsw i64 %i, 1
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%exitcond = icmp eq i64 %inc, 156250000
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br i1 %exitcond, label %ret, label %loop
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ret:
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ret i64 %s2
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}
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; This loop contains a cvtsi2sd instruction that has a loop-carried
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; false dependency on an xmm that is modified by other scalar instructions
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; that follow it in the loop. Additionally, the source of convert is a
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@ -115,7 +148,7 @@ for.end: ; preds = %for.body, %entry
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@w = common global [1024 x double] zeroinitializer, align 16
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@v = common global [1024 x i32] zeroinitializer, align 16
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define void @loopdep2() {
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define void @loopdep3() {
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entry:
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br label %for.cond1.preheader
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@ -151,11 +184,18 @@ for.inc14: ; preds = %for.body3
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for.end16: ; preds = %for.inc14
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ret void
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;CHECK-LABEL:@loopdep2
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;CHECK: xorps [[XMM0:%xmm[0-9]+]], [[XMM0]]
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;CHECK-NEXT: cvtsi2sdl {{.*}}, [[XMM0]]
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;CHECK-NEXT: mulsd {{.*}}, [[XMM0]]
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;CHECK-NEXT: mulsd {{.*}}, [[XMM0]]
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;CHECK-NEXT: mulsd {{.*}}, [[XMM0]]
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;CHECK-NEXT: movsd [[XMM0]],
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;SSE-LABEL:@loopdep3
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;SSE: xorps [[XMM0:%xmm[0-9]+]], [[XMM0]]
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;SSE-NEXT: cvtsi2sdl {{.*}}, [[XMM0]]
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;SSE-NEXT: mulsd {{.*}}, [[XMM0]]
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;SSE-NEXT: mulsd {{.*}}, [[XMM0]]
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;SSE-NEXT: mulsd {{.*}}, [[XMM0]]
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;SSE-NEXT: movsd [[XMM0]],
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;AVX-LABEL:@loopdep3
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;AVX: vxorps [[XMM0:%xmm[0-9]+]], [[XMM0]]
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;AVX-NEXT: vcvtsi2sdl {{.*}}, [[XMM0]], [[XMM0]]
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;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]]
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;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]]
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;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]]
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;AVX-NEXT: vmovsd [[XMM0]],
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}
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