Make x86 test actually test x86 code generation. Fix the

construct on ARM, which was breaking by coincidence, and add a similar 
testcase for ARM.

llvm-svn: 79719

llvm/lib/Target/ARM/ARMISelLowering.cpp

@@ -2134,8 +2134,11 @@ static SDValue LowerShift(SDNode *N, SelectionDAG &DAG,
                        N->getOperand(0), NegatedCount);
   }
 
-  assert(VT == MVT::i64 &&
-         (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
+  // We can get here for a node like i32 = ISD::SHL i32, i64
+  if (VT != MVT::i64)
+    return SDValue();
+
+  assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
          "Unknown shift to lower!");
 
   // We only lower SRA, SRL of 1 here, all others use generic lowering.

llvm/test/CodeGen/ARM/vshift_split.ll

@@ -0,0 +1,8 @@
+; RUN: llvm-as < %s | llc -march=arm -mattr=-neon
+
+; Example that requires splitting and expanding a vector shift.
+define <2 x i64> @update(<2 x i64> %val) nounwind readnone {
+entry:
+	%shr = lshr <2 x i64> %val, < i64 2, i64 2 >		; <<2 x i64>> [#uses=1]
+	ret <2 x i64> %shr
+}

llvm/test/CodeGen/X86/vshift_split.ll

@@ -1,8 +1,8 @@
-; RUN: llvm-as < %s | llc
+; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2
 
 ; Example that requires splitting and expanding a vector shift.
 define <2 x i64> @update(<2 x i64> %val) nounwind readnone {
 entry:
-	%shr = lshr <2 x i64> %val, < i64 2, i64 2 >		; <<2 x i64>> [#uses=1]
+	%shr = lshr <2 x i64> %val, < i64 2, i64 3 >
 	ret <2 x i64> %shr
 }