forked from OSchip/llvm-project
[TargetLowering] Only demand a rotation's modulo amount bits
ISD::ROTL/ROTR rotation values are guaranteed to act as a modulo amount, so for power-of-2 bitwidths we only need the lowest bits. Differential Revision: https://reviews.llvm.org/D76201
This commit is contained in:
Simon Pilgrim
parent
c45eaeabb7
commit
68224c1952
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@ -1647,10 +1647,19 @@ bool TargetLowering::SimplifyDemandedBits(
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case ISD::ROTL:
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case ISD::ROTR: {
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SDValue Op0 = Op.getOperand(0);
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SDValue Op1 = Op.getOperand(1);
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// If we're rotating an 0/-1 value, then it stays an 0/-1 value.
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if (BitWidth == TLO.DAG.ComputeNumSignBits(Op0, DemandedElts, Depth + 1))
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return TLO.CombineTo(Op, Op0);
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// For pow-2 bitwidths we only demand the bottom modulo amt bits.
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if (isPowerOf2_32(BitWidth)) {
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APInt DemandedAmtBits(Op1.getScalarValueSizeInBits(), BitWidth - 1);
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if (SimplifyDemandedBits(Op1, DemandedAmtBits, DemandedElts, Known2, TLO,
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Depth + 1))
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return true;
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}
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break;
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}
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case ISD::BITREVERSE: {
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@ -284,6 +284,8 @@ SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
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const SDNode *N = Op.getNode();
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EVT VT = Op.getValueType();
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SDLoc dl(N);
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assert(isPowerOf2_32(VT.getSizeInBits()) &&
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"Expected power-of-2 shift amount");
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// Expand non-constant shifts to loops.
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if (!isa<ConstantSDNode>(N->getOperand(1))) {
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@ -296,12 +298,20 @@ SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
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case ISD::SRL:
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return DAG.getNode(AVRISD::LSRLOOP, dl, VT, N->getOperand(0),
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N->getOperand(1));
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case ISD::ROTL:
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return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0),
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N->getOperand(1));
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case ISD::ROTR:
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return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0),
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N->getOperand(1));
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case ISD::ROTL: {
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SDValue Amt = N->getOperand(1);
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EVT AmtVT = Amt.getValueType();
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Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
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DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
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return DAG.getNode(AVRISD::ROLLOOP, dl, VT, N->getOperand(0), Amt);
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}
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case ISD::ROTR: {
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SDValue Amt = N->getOperand(1);
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EVT AmtVT = Amt.getValueType();
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Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt,
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DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT));
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return DAG.getNode(AVRISD::RORLOOP, dl, VT, N->getOperand(0), Amt);
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}
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case ISD::SRA:
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return DAG.getNode(AVRISD::ASRLOOP, dl, VT, N->getOperand(0),
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N->getOperand(1));
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@ -317,9 +327,11 @@ SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
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break;
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case ISD::ROTL:
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Opc8 = AVRISD::ROL;
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ShiftAmount = ShiftAmount % VT.getSizeInBits();
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break;
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case ISD::ROTR:
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Opc8 = AVRISD::ROR;
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ShiftAmount = ShiftAmount % VT.getSizeInBits();
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break;
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case ISD::SRL:
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Opc8 = AVRISD::LSR;
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@ -65,7 +65,7 @@ define i32 @rotl_i32(i32 %x, i32 %z) {
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define i64 @rotl_i64(i64 %x, i64 %z) {
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; CHECK-LABEL: rotl_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: neg x8, x1
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; CHECK-NEXT: neg w8, w1
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; CHECK-NEXT: ror x0, x0, x8
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; CHECK-NEXT: ret
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%f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %z)
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@ -4,7 +4,6 @@
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define i32 @rotl32(i32 %A, i8 %Amt) nounwind {
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; CHECK-LABEL: rotl32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: clrlwi 4, 4, 24
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; CHECK-NEXT: rotlw 3, 3, 4
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; CHECK-NEXT: blr
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%shift.upgrd.1 = zext i8 %Amt to i32 ; <i32> [#uses=1]
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@ -20,7 +19,6 @@ define i32 @rotr32(i32 %A, i8 %Amt) nounwind {
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; CHECK-LABEL: rotr32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: subfic 4, 4, 32
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; CHECK-NEXT: clrlwi 4, 4, 24
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; CHECK-NEXT: rotlw 3, 3, 4
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; CHECK-NEXT: blr
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%shift.upgrd.3 = zext i8 %Amt to i32 ; <i32> [#uses=1]
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@ -7,10 +7,10 @@
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define i32 @f1(i32 %val, i32 %amt) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nill %r3, 31
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; CHECK-NEXT: nill %r3, 15
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; CHECK-NEXT: rll %r2, %r2, 0(%r3)
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; CHECK-NEXT: br %r14
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%mod = urem i32 %amt, 32
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%mod = urem i32 %amt, 16
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%inv = sub i32 32, %mod
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%parta = shl i32 %val, %mod
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@ -4,14 +4,14 @@
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Test that AND is not removed when some lower 6 bits are not set.
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; Test that AND is not removed when some lower 5 bits are not set.
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define i32 @f1(i32 %val, i32 %amt) {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: nill %r3, 31
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; CHECK-NEXT: nill %r3, 15
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; CHECK-NEXT: rll %r2, %r2, 0(%r3)
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; CHECK-NEXT: br %r14
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%and = and i32 %amt, 31
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%and = and i32 %amt, 15
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%inv = sub i32 32, %and
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%parta = shl i32 %val, %and
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@ -97,12 +97,12 @@ define i32 @f7(i32 %a, i64 %amt) {
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ret i32 %or
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}
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; Check shift amounts that have the largest in-range constant term. We could
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; mask the amount instead.
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; Check shift amounts that have the largest in-range constant term, and then
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; mask the amount.
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define i32 @f8(i32 %a, i32 %amt) {
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; CHECK-LABEL: f8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rll %r2, %r2, 524287(%r3)
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; CHECK-NEXT: rll %r2, %r2, -1(%r3)
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; CHECK-NEXT: br %r14
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%add = add i32 %amt, 524287
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%sub = sub i32 32, %add
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@ -157,13 +157,11 @@ define i32 @f11(i32 %a, i32 %amt) {
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ret i32 %or
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}
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; Check the next value down, which without masking must use a separate
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; addition.
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; Check the next value down, masking the amount removes the addition.
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define i32 @f12(i32 %a, i32 %amt) {
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; CHECK-LABEL: f12:
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; CHECK: # %bb.0:
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; CHECK-NEXT: afi %r3, -524289
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; CHECK-NEXT: rll %r2, %r2, 0(%r3)
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; CHECK-NEXT: rll %r2, %r2, -1(%r3)
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; CHECK-NEXT: br %r14
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%suba = sub i32 %amt, 524289
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%subb = sub i32 32, %suba
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@ -98,12 +98,12 @@ define i64 @f7(i64 %a, i32 %amt) {
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ret i64 %or
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}
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; Check shift amounts that have the largest in-range constant term. We could
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; mask the amount instead.
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; Check shift amounts that have the largest in-range constant term, and then
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; mask the amount.
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define i64 @f8(i64 %a, i64 %amt) {
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; CHECK-LABEL: f8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: rllg %r2, %r2, 524287(%r3)
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; CHECK-NEXT: rllg %r2, %r2, -1(%r3)
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; CHECK-NEXT: br %r14
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%add = add i64 %amt, 524287
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%sub = sub i64 64, %add
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@ -158,13 +158,11 @@ define i64 @f11(i64 %a, i64 %amt) {
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ret i64 %or
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}
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; Check the next value down, which without masking must use a separate
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; addition.
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; Check the next value down, masking the amount removes the addition.
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define i64 @f12(i64 %a, i64 %amt) {
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; CHECK-LABEL: f12:
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; CHECK: # %bb.0:
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; CHECK-NEXT: afi %r3, -524289
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; CHECK-NEXT: rllg %r2, %r2, 0(%r3)
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; CHECK-NEXT: rllg %r2, %r2, -1(%r3)
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; CHECK-NEXT: br %r14
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%suba = sub i64 %amt, 524289
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%subb = sub i64 64, %suba
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@ -27,9 +27,7 @@ define i32 @f2(i32 %v, i32 %nbits) {
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;
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; THUMB1-LABEL: f2:
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; THUMB1: @ %bb.0: @ %entry
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; THUMB1-NEXT: movs r2, #31
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; THUMB1-NEXT: ands r2, r1
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; THUMB1-NEXT: rors r0, r2
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; THUMB1-NEXT: rors r0, r1
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; THUMB1-NEXT: bx lr
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entry:
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%and = and i32 %nbits, 31
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@ -118,57 +118,55 @@ define i32 @combine_rot_select_zero(i32, i32) {
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define <4 x i32> @combine_vec_rot_select_zero(<4 x i32>, <4 x i32>) {
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; SSE2-LABEL: combine_vec_rot_select_zero:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [31,31,31,31]
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; SSE2-NEXT: pand %xmm1, %xmm2
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; SSE2-NEXT: pxor %xmm3, %xmm3
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; SSE2-NEXT: pslld $23, %xmm2
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; SSE2-NEXT: paddd {{.*}}(%rip), %xmm2
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; SSE2-NEXT: cvttps2dq %xmm2, %xmm2
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; SSE2-NEXT: pxor %xmm2, %xmm2
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; SSE2-NEXT: movdqa {{.*#+}} xmm3 = [31,31,31,31]
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; SSE2-NEXT: pand %xmm1, %xmm3
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; SSE2-NEXT: pslld $23, %xmm3
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; SSE2-NEXT: paddd {{.*}}(%rip), %xmm3
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; SSE2-NEXT: cvttps2dq %xmm3, %xmm3
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; SSE2-NEXT: movdqa %xmm0, %xmm4
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; SSE2-NEXT: pmuludq %xmm2, %xmm4
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; SSE2-NEXT: pmuludq %xmm3, %xmm4
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; SSE2-NEXT: pshufd {{.*#+}} xmm5 = xmm4[1,3,2,3]
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; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm0[1,1,3,3]
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
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; SSE2-NEXT: pmuludq %xmm6, %xmm2
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; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm2[1,3,2,3]
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; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
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; SSE2-NEXT: pmuludq %xmm6, %xmm3
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; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm3[1,3,2,3]
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; SSE2-NEXT: punpckldq {{.*#+}} xmm5 = xmm5[0],xmm6[0],xmm5[1],xmm6[1]
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; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
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; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
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; SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm2[0],xmm4[1],xmm2[1]
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; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
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; SSE2-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm3[0],xmm4[1],xmm3[1]
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; SSE2-NEXT: por %xmm5, %xmm4
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; SSE2-NEXT: pcmpeqd %xmm1, %xmm3
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; SSE2-NEXT: pand %xmm3, %xmm0
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; SSE2-NEXT: pandn %xmm4, %xmm3
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; SSE2-NEXT: por %xmm3, %xmm0
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; SSE2-NEXT: pcmpeqd %xmm1, %xmm2
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; SSE2-NEXT: pand %xmm2, %xmm0
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; SSE2-NEXT: pandn %xmm4, %xmm2
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; SSE2-NEXT: por %xmm2, %xmm0
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; SSE2-NEXT: retq
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;
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; XOP-LABEL: combine_vec_rot_select_zero:
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; XOP: # %bb.0:
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; XOP-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm2
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; XOP-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; XOP-NEXT: vprotd %xmm2, %xmm0, %xmm2
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; XOP-NEXT: vpcomeqd %xmm3, %xmm1, %xmm1
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; XOP-NEXT: vblendvps %xmm1, %xmm0, %xmm2, %xmm0
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; XOP-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; XOP-NEXT: vprotd %xmm1, %xmm0, %xmm3
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; XOP-NEXT: vpcomeqd %xmm2, %xmm1, %xmm1
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; XOP-NEXT: vblendvps %xmm1, %xmm0, %xmm3, %xmm0
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; XOP-NEXT: retq
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;
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; AVX2-LABEL: combine_vec_rot_select_zero:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [31,31,31,31]
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; AVX2-NEXT: vpand %xmm2, %xmm1, %xmm2
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; AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3
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; AVX2-NEXT: vpsllvd %xmm2, %xmm0, %xmm4
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; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm3 = [31,31,31,31]
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; AVX2-NEXT: vpand %xmm3, %xmm1, %xmm3
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; AVX2-NEXT: vpsllvd %xmm3, %xmm0, %xmm4
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm5 = [32,32,32,32]
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; AVX2-NEXT: vpsubd %xmm2, %xmm5, %xmm2
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; AVX2-NEXT: vpsrlvd %xmm2, %xmm0, %xmm2
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; AVX2-NEXT: vpor %xmm2, %xmm4, %xmm2
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; AVX2-NEXT: vpcmpeqd %xmm3, %xmm1, %xmm1
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; AVX2-NEXT: vblendvps %xmm1, %xmm0, %xmm2, %xmm0
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; AVX2-NEXT: vpsubd %xmm3, %xmm5, %xmm3
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; AVX2-NEXT: vpsrlvd %xmm3, %xmm0, %xmm3
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; AVX2-NEXT: vpor %xmm3, %xmm4, %xmm3
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; AVX2-NEXT: vpcmpeqd %xmm2, %xmm1, %xmm1
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; AVX2-NEXT: vblendvps %xmm1, %xmm0, %xmm3, %xmm0
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; AVX2-NEXT: retq
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;
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; AVX512-LABEL: combine_vec_rot_select_zero:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm1, %xmm2
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; AVX512-NEXT: vprolvd %xmm2, %xmm0, %xmm2
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; AVX512-NEXT: vprolvd %xmm1, %xmm0, %xmm2
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; AVX512-NEXT: vptestnmd %xmm1, %xmm1, %k1
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; AVX512-NEXT: vmovdqa32 %xmm0, %xmm2 {%k1}
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; AVX512-NEXT: vmovdqa %xmm2, %xmm0
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@ -310,14 +308,13 @@ define <4 x i32> @rotate_demanded_bits_3(<4 x i32>, <4 x i32>) {
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; XOP-LABEL: rotate_demanded_bits_3:
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; XOP: # %bb.0:
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; XOP-NEXT: vpaddd %xmm1, %xmm1, %xmm1
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; XOP-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
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; XOP-NEXT: vprotd %xmm1, %xmm0, %xmm0
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; XOP-NEXT: retq
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;
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; AVX2-LABEL: rotate_demanded_bits_3:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpaddd %xmm1, %xmm1, %xmm1
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [30,30,30,30]
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [31,31,31,31]
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; AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1
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; AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm2
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm3 = [32,32,32,32]
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@ -329,7 +326,6 @@ define <4 x i32> @rotate_demanded_bits_3(<4 x i32>, <4 x i32>) {
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; AVX512-LABEL: rotate_demanded_bits_3:
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; AVX512: # %bb.0:
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; AVX512-NEXT: vpaddd %xmm1, %xmm1, %xmm1
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; AVX512-NEXT: vpandd {{.*}}(%rip){1to4}, %xmm1, %xmm1
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; AVX512-NEXT: vprolvd %xmm1, %xmm0, %xmm0
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; AVX512-NEXT: retq
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%3 = shl <4 x i32> %1, <i32 1, i32 1, i32 1, i32 1>
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@ -124,23 +124,21 @@ define <64 x i8> @var_funnnel_v64i8(<64 x i8> %x, <64 x i8> %amt) nounwind {
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; AVX512F-NEXT: vpsllw $4, %ymm3, %ymm6
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; AVX512F-NEXT: vpand %ymm5, %ymm6, %ymm6
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; AVX512F-NEXT: vpor %ymm4, %ymm6, %ymm4
|
||||
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm6 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
|
||||
; AVX512F-NEXT: vpand %ymm6, %ymm2, %ymm2
|
||||
; AVX512F-NEXT: vpsllw $5, %ymm2, %ymm2
|
||||
; AVX512F-NEXT: vpblendvb %ymm2, %ymm4, %ymm3, %ymm3
|
||||
; AVX512F-NEXT: vpsrlw $6, %ymm3, %ymm4
|
||||
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm7 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
|
||||
; AVX512F-NEXT: vpandn %ymm4, %ymm7, %ymm4
|
||||
; AVX512F-NEXT: vpsllw $2, %ymm3, %ymm8
|
||||
; AVX512F-NEXT: vpand %ymm7, %ymm8, %ymm8
|
||||
; AVX512F-NEXT: vpor %ymm4, %ymm8, %ymm4
|
||||
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm6 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
|
||||
; AVX512F-NEXT: vpandn %ymm4, %ymm6, %ymm4
|
||||
; AVX512F-NEXT: vpsllw $2, %ymm3, %ymm7
|
||||
; AVX512F-NEXT: vpand %ymm6, %ymm7, %ymm7
|
||||
; AVX512F-NEXT: vpor %ymm4, %ymm7, %ymm4
|
||||
; AVX512F-NEXT: vpaddb %ymm2, %ymm2, %ymm2
|
||||
; AVX512F-NEXT: vpblendvb %ymm2, %ymm4, %ymm3, %ymm3
|
||||
; AVX512F-NEXT: vpsrlw $7, %ymm3, %ymm4
|
||||
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm8 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
|
||||
; AVX512F-NEXT: vpand %ymm4, %ymm8, %ymm4
|
||||
; AVX512F-NEXT: vpaddb %ymm3, %ymm3, %ymm9
|
||||
; AVX512F-NEXT: vpor %ymm4, %ymm9, %ymm4
|
||||
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm7 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
|
||||
; AVX512F-NEXT: vpand %ymm7, %ymm4, %ymm4
|
||||
; AVX512F-NEXT: vpaddb %ymm3, %ymm3, %ymm8
|
||||
; AVX512F-NEXT: vpor %ymm4, %ymm8, %ymm4
|
||||
; AVX512F-NEXT: vpaddb %ymm2, %ymm2, %ymm2
|
||||
; AVX512F-NEXT: vpblendvb %ymm2, %ymm4, %ymm3, %ymm2
|
||||
; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm3
|
||||
|
|
@ -148,18 +146,17 @@ define <64 x i8> @var_funnnel_v64i8(<64 x i8> %x, <64 x i8> %amt) nounwind {
|
|||
; AVX512F-NEXT: vpsllw $4, %ymm0, %ymm4
|
||||
; AVX512F-NEXT: vpand %ymm5, %ymm4, %ymm4
|
||||
; AVX512F-NEXT: vpor %ymm3, %ymm4, %ymm3
|
||||
; AVX512F-NEXT: vpand %ymm6, %ymm1, %ymm1
|
||||
; AVX512F-NEXT: vpsllw $5, %ymm1, %ymm1
|
||||
; AVX512F-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
|
||||
; AVX512F-NEXT: vpsrlw $6, %ymm0, %ymm3
|
||||
; AVX512F-NEXT: vpandn %ymm3, %ymm7, %ymm3
|
||||
; AVX512F-NEXT: vpandn %ymm3, %ymm6, %ymm3
|
||||
; AVX512F-NEXT: vpsllw $2, %ymm0, %ymm4
|
||||
; AVX512F-NEXT: vpand %ymm7, %ymm4, %ymm4
|
||||
; AVX512F-NEXT: vpand %ymm6, %ymm4, %ymm4
|
||||
; AVX512F-NEXT: vpor %ymm3, %ymm4, %ymm3
|
||||
; AVX512F-NEXT: vpaddb %ymm1, %ymm1, %ymm1
|
||||
; AVX512F-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
|
||||
; AVX512F-NEXT: vpsrlw $7, %ymm0, %ymm3
|
||||
; AVX512F-NEXT: vpand %ymm3, %ymm8, %ymm3
|
||||
; AVX512F-NEXT: vpand %ymm7, %ymm3, %ymm3
|
||||
; AVX512F-NEXT: vpaddb %ymm0, %ymm0, %ymm4
|
||||
; AVX512F-NEXT: vpor %ymm3, %ymm4, %ymm3
|
||||
; AVX512F-NEXT: vpaddb %ymm1, %ymm1, %ymm1
|
||||
|
|
@ -175,36 +172,33 @@ define <64 x i8> @var_funnnel_v64i8(<64 x i8> %x, <64 x i8> %amt) nounwind {
|
|||
; AVX512VL-NEXT: vpsllw $4, %ymm3, %ymm5
|
||||
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm6 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]
|
||||
; AVX512VL-NEXT: vpternlogq $226, %ymm4, %ymm6, %ymm5
|
||||
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm4 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
|
||||
; AVX512VL-NEXT: vpand %ymm4, %ymm2, %ymm2
|
||||
; AVX512VL-NEXT: vpsllw $5, %ymm2, %ymm2
|
||||
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm5, %ymm3, %ymm3
|
||||
; AVX512VL-NEXT: vpsrlw $6, %ymm3, %ymm5
|
||||
; AVX512VL-NEXT: vpsllw $2, %ymm3, %ymm7
|
||||
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm8 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
|
||||
; AVX512VL-NEXT: vpternlogq $226, %ymm5, %ymm8, %ymm7
|
||||
; AVX512VL-NEXT: vpsrlw $6, %ymm3, %ymm4
|
||||
; AVX512VL-NEXT: vpsllw $2, %ymm3, %ymm5
|
||||
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm7 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
|
||||
; AVX512VL-NEXT: vpternlogq $226, %ymm4, %ymm7, %ymm5
|
||||
; AVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm2
|
||||
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm7, %ymm3, %ymm3
|
||||
; AVX512VL-NEXT: vpsrlw $7, %ymm3, %ymm5
|
||||
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm7 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
|
||||
; AVX512VL-NEXT: vpand %ymm7, %ymm5, %ymm5
|
||||
; AVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm9
|
||||
; AVX512VL-NEXT: vpor %ymm5, %ymm9, %ymm5
|
||||
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm5, %ymm3, %ymm3
|
||||
; AVX512VL-NEXT: vpsrlw $7, %ymm3, %ymm4
|
||||
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm5 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
|
||||
; AVX512VL-NEXT: vpand %ymm5, %ymm4, %ymm4
|
||||
; AVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm8
|
||||
; AVX512VL-NEXT: vpor %ymm4, %ymm8, %ymm4
|
||||
; AVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm2
|
||||
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm5, %ymm3, %ymm2
|
||||
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm4, %ymm3, %ymm2
|
||||
; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm3
|
||||
; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm5
|
||||
; AVX512VL-NEXT: vpternlogq $226, %ymm3, %ymm6, %ymm5
|
||||
; AVX512VL-NEXT: vpand %ymm4, %ymm1, %ymm1
|
||||
; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm4
|
||||
; AVX512VL-NEXT: vpternlogq $226, %ymm3, %ymm6, %ymm4
|
||||
; AVX512VL-NEXT: vpsllw $5, %ymm1, %ymm1
|
||||
; AVX512VL-NEXT: vpblendvb %ymm1, %ymm5, %ymm0, %ymm0
|
||||
; AVX512VL-NEXT: vpblendvb %ymm1, %ymm4, %ymm0, %ymm0
|
||||
; AVX512VL-NEXT: vpsrlw $6, %ymm0, %ymm3
|
||||
; AVX512VL-NEXT: vpsllw $2, %ymm0, %ymm4
|
||||
; AVX512VL-NEXT: vpternlogq $226, %ymm3, %ymm8, %ymm4
|
||||
; AVX512VL-NEXT: vpternlogq $226, %ymm3, %ymm7, %ymm4
|
||||
; AVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm1
|
||||
; AVX512VL-NEXT: vpblendvb %ymm1, %ymm4, %ymm0, %ymm0
|
||||
; AVX512VL-NEXT: vpsrlw $7, %ymm0, %ymm3
|
||||
; AVX512VL-NEXT: vpand %ymm7, %ymm3, %ymm3
|
||||
; AVX512VL-NEXT: vpand %ymm5, %ymm3, %ymm3
|
||||
; AVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm4
|
||||
; AVX512VL-NEXT: vpor %ymm3, %ymm4, %ymm3
|
||||
; AVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm1
|
||||
|
|
|
|||
|
|
@ -132,23 +132,21 @@ define <64 x i8> @var_funnnel_v64i8(<64 x i8> %x, <64 x i8> %amt) nounwind {
|
|||
; AVX512F-NEXT: vpor %ymm4, %ymm6, %ymm4
|
||||
; AVX512F-NEXT: vpxor %xmm6, %xmm6, %xmm6
|
||||
; AVX512F-NEXT: vpsubb %ymm2, %ymm6, %ymm2
|
||||
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm7 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
|
||||
; AVX512F-NEXT: vpand %ymm7, %ymm2, %ymm2
|
||||
; AVX512F-NEXT: vpsllw $5, %ymm2, %ymm2
|
||||
; AVX512F-NEXT: vpblendvb %ymm2, %ymm4, %ymm3, %ymm3
|
||||
; AVX512F-NEXT: vpsrlw $6, %ymm3, %ymm4
|
||||
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm8 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
|
||||
; AVX512F-NEXT: vpandn %ymm4, %ymm8, %ymm4
|
||||
; AVX512F-NEXT: vpsllw $2, %ymm3, %ymm9
|
||||
; AVX512F-NEXT: vpand %ymm8, %ymm9, %ymm9
|
||||
; AVX512F-NEXT: vpor %ymm4, %ymm9, %ymm4
|
||||
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm7 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
|
||||
; AVX512F-NEXT: vpandn %ymm4, %ymm7, %ymm4
|
||||
; AVX512F-NEXT: vpsllw $2, %ymm3, %ymm8
|
||||
; AVX512F-NEXT: vpand %ymm7, %ymm8, %ymm8
|
||||
; AVX512F-NEXT: vpor %ymm4, %ymm8, %ymm4
|
||||
; AVX512F-NEXT: vpaddb %ymm2, %ymm2, %ymm2
|
||||
; AVX512F-NEXT: vpblendvb %ymm2, %ymm4, %ymm3, %ymm3
|
||||
; AVX512F-NEXT: vpsrlw $7, %ymm3, %ymm4
|
||||
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm9 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
|
||||
; AVX512F-NEXT: vpand %ymm4, %ymm9, %ymm4
|
||||
; AVX512F-NEXT: vpaddb %ymm3, %ymm3, %ymm10
|
||||
; AVX512F-NEXT: vpor %ymm4, %ymm10, %ymm4
|
||||
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm8 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
|
||||
; AVX512F-NEXT: vpand %ymm4, %ymm8, %ymm4
|
||||
; AVX512F-NEXT: vpaddb %ymm3, %ymm3, %ymm9
|
||||
; AVX512F-NEXT: vpor %ymm4, %ymm9, %ymm4
|
||||
; AVX512F-NEXT: vpaddb %ymm2, %ymm2, %ymm2
|
||||
; AVX512F-NEXT: vpblendvb %ymm2, %ymm4, %ymm3, %ymm2
|
||||
; AVX512F-NEXT: vpsrlw $4, %ymm0, %ymm3
|
||||
|
|
@ -157,18 +155,17 @@ define <64 x i8> @var_funnnel_v64i8(<64 x i8> %x, <64 x i8> %amt) nounwind {
|
|||
; AVX512F-NEXT: vpand %ymm5, %ymm4, %ymm4
|
||||
; AVX512F-NEXT: vpor %ymm3, %ymm4, %ymm3
|
||||
; AVX512F-NEXT: vpsubb %ymm1, %ymm6, %ymm1
|
||||
; AVX512F-NEXT: vpand %ymm7, %ymm1, %ymm1
|
||||
; AVX512F-NEXT: vpsllw $5, %ymm1, %ymm1
|
||||
; AVX512F-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
|
||||
; AVX512F-NEXT: vpsrlw $6, %ymm0, %ymm3
|
||||
; AVX512F-NEXT: vpandn %ymm3, %ymm8, %ymm3
|
||||
; AVX512F-NEXT: vpandn %ymm3, %ymm7, %ymm3
|
||||
; AVX512F-NEXT: vpsllw $2, %ymm0, %ymm4
|
||||
; AVX512F-NEXT: vpand %ymm4, %ymm8, %ymm4
|
||||
; AVX512F-NEXT: vpand %ymm7, %ymm4, %ymm4
|
||||
; AVX512F-NEXT: vpor %ymm3, %ymm4, %ymm3
|
||||
; AVX512F-NEXT: vpaddb %ymm1, %ymm1, %ymm1
|
||||
; AVX512F-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm0
|
||||
; AVX512F-NEXT: vpsrlw $7, %ymm0, %ymm3
|
||||
; AVX512F-NEXT: vpand %ymm3, %ymm9, %ymm3
|
||||
; AVX512F-NEXT: vpand %ymm3, %ymm8, %ymm3
|
||||
; AVX512F-NEXT: vpaddb %ymm0, %ymm0, %ymm4
|
||||
; AVX512F-NEXT: vpor %ymm3, %ymm4, %ymm3
|
||||
; AVX512F-NEXT: vpaddb %ymm1, %ymm1, %ymm1
|
||||
|
|
@ -186,37 +183,34 @@ define <64 x i8> @var_funnnel_v64i8(<64 x i8> %x, <64 x i8> %amt) nounwind {
|
|||
; AVX512VL-NEXT: vpternlogq $226, %ymm4, %ymm6, %ymm5
|
||||
; AVX512VL-NEXT: vpxor %xmm4, %xmm4, %xmm4
|
||||
; AVX512VL-NEXT: vpsubb %ymm2, %ymm4, %ymm2
|
||||
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm7 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7]
|
||||
; AVX512VL-NEXT: vpand %ymm7, %ymm2, %ymm2
|
||||
; AVX512VL-NEXT: vpsllw $5, %ymm2, %ymm2
|
||||
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm5, %ymm3, %ymm3
|
||||
; AVX512VL-NEXT: vpsrlw $6, %ymm3, %ymm5
|
||||
; AVX512VL-NEXT: vpsllw $2, %ymm3, %ymm8
|
||||
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm9 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
|
||||
; AVX512VL-NEXT: vpternlogq $226, %ymm5, %ymm9, %ymm8
|
||||
; AVX512VL-NEXT: vpsllw $2, %ymm3, %ymm7
|
||||
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm8 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]
|
||||
; AVX512VL-NEXT: vpternlogq $226, %ymm5, %ymm8, %ymm7
|
||||
; AVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm2
|
||||
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm8, %ymm3, %ymm3
|
||||
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm7, %ymm3, %ymm3
|
||||
; AVX512VL-NEXT: vpsrlw $7, %ymm3, %ymm5
|
||||
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm8 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
|
||||
; AVX512VL-NEXT: vpand %ymm5, %ymm8, %ymm5
|
||||
; AVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm10
|
||||
; AVX512VL-NEXT: vpor %ymm5, %ymm10, %ymm5
|
||||
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm7 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
|
||||
; AVX512VL-NEXT: vpand %ymm7, %ymm5, %ymm5
|
||||
; AVX512VL-NEXT: vpaddb %ymm3, %ymm3, %ymm9
|
||||
; AVX512VL-NEXT: vpor %ymm5, %ymm9, %ymm5
|
||||
; AVX512VL-NEXT: vpaddb %ymm2, %ymm2, %ymm2
|
||||
; AVX512VL-NEXT: vpblendvb %ymm2, %ymm5, %ymm3, %ymm2
|
||||
; AVX512VL-NEXT: vpsrlw $4, %ymm0, %ymm3
|
||||
; AVX512VL-NEXT: vpsllw $4, %ymm0, %ymm5
|
||||
; AVX512VL-NEXT: vpternlogq $226, %ymm3, %ymm6, %ymm5
|
||||
; AVX512VL-NEXT: vpsubb %ymm1, %ymm4, %ymm1
|
||||
; AVX512VL-NEXT: vpand %ymm7, %ymm1, %ymm1
|
||||
; AVX512VL-NEXT: vpsllw $5, %ymm1, %ymm1
|
||||
; AVX512VL-NEXT: vpblendvb %ymm1, %ymm5, %ymm0, %ymm0
|
||||
; AVX512VL-NEXT: vpsrlw $6, %ymm0, %ymm3
|
||||
; AVX512VL-NEXT: vpsllw $2, %ymm0, %ymm4
|
||||
; AVX512VL-NEXT: vpternlogq $226, %ymm3, %ymm9, %ymm4
|
||||
; AVX512VL-NEXT: vpternlogq $226, %ymm3, %ymm8, %ymm4
|
||||
; AVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm1
|
||||
; AVX512VL-NEXT: vpblendvb %ymm1, %ymm4, %ymm0, %ymm0
|
||||
; AVX512VL-NEXT: vpsrlw $7, %ymm0, %ymm3
|
||||
; AVX512VL-NEXT: vpand %ymm3, %ymm8, %ymm3
|
||||
; AVX512VL-NEXT: vpand %ymm7, %ymm3, %ymm3
|
||||
; AVX512VL-NEXT: vpaddb %ymm0, %ymm0, %ymm4
|
||||
; AVX512VL-NEXT: vpor %ymm3, %ymm4, %ymm3
|
||||
; AVX512VL-NEXT: vpaddb %ymm1, %ymm1, %ymm1
|
||||
|
|
|
|||
Loading…
Reference in New Issue