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fix PR7518 - terrible codegen of <2 x float>, by only marking 

v2f32 as legal in 32-bit mode.  It is just as terrible there,
but I just care about x86-64 and noone claims it is valuable
in 64-bit mode.

llvm-svn: 107600
This commit is contained in:
Chris Lattner 2010-07-04 22:57:10 +00:00
parent cb948d3329
commit 681b926d54
2 changed files with 32 additions and 6 deletions
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10
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -617,6 +617,11 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
addRegisterClass(MVT::v8i8, X86::VR64RegisterClass, false);
addRegisterClass(MVT::v4i16, X86::VR64RegisterClass, false);
addRegisterClass(MVT::v2i32, X86::VR64RegisterClass, false);
// FIXME: v2f32 isn't an MMX type. We currently claim that it is legal
// because of some ABI issue, but this isn't the right fix.
bool IsV2F32Legal = !Subtarget->is64Bit();
if (IsV2F32Legal)
addRegisterClass(MVT::v2f32, X86::VR64RegisterClass, false);
addRegisterClass(MVT::v1i64, X86::VR64RegisterClass, false);
@ -663,13 +668,16 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64);
setOperationAction(ISD::LOAD, MVT::v2i32, Promote);
AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64);
if (IsV2F32Legal) {
setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64);
}
setOperationAction(ISD::LOAD, MVT::v1i64, Legal);
setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom);
setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom);
setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom);
if (IsV2F32Legal)
setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom);
setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom);
@ -678,6 +686,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom);
if (IsV2F32Legal)
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom);
setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom);
@ -697,6 +706,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
setOperationAction(ISD::BIT_CONVERT, MVT::v8i8, Custom);
setOperationAction(ISD::BIT_CONVERT, MVT::v4i16, Custom);
setOperationAction(ISD::BIT_CONVERT, MVT::v2i32, Custom);
if (IsV2F32Legal)
setOperationAction(ISD::BIT_CONVERT, MVT::v2f32, Custom);
setOperationAction(ISD::BIT_CONVERT, MVT::v1i64, Custom);
}

16
llvm/test/CodeGen/X86/v2f32.ll Normal file
View File

@ -0,0 +1,16 @@
; RUN: llc < %s -march=x86-64 -asm-verbose=0 -o - | FileCheck %s
; PR7518
define void @test1(<2 x float> %Q, float *%P2) nounwind {
%a = extractelement <2 x float> %Q, i32 0
%b = extractelement <2 x float> %Q, i32 1
%c = fadd float %a, %b
store float %c, float* %P2
ret void
; CHECK: test1:
; CHECK-NEXT: addss %xmm1, %xmm0
; CHECK-NEXT: movss %xmm0, (%rdi)
; CHECK-NEXT: ret
}