forked from OSchip/llvm-project
[X86][AVX] Dropped combineShuffle256 - this can now be performed by EltsFromConsecutiveLoads
llvm-svn: 279397
This commit is contained in:
parent
792636603f
commit
67e7e22462
llvm/lib/Target/X86
|
@ -24823,83 +24823,6 @@ bool X86TargetLowering::isGAPlusOffset(SDNode *N,
|
|||
return TargetLowering::isGAPlusOffset(N, GA, Offset);
|
||||
}
|
||||
|
||||
/// Performs shuffle combines for 256-bit vectors.
|
||||
/// FIXME: This could be expanded to support 512 bit vectors as well.
|
||||
static SDValue combineShuffle256(SDNode *N, SelectionDAG &DAG,
|
||||
TargetLowering::DAGCombinerInfo &DCI,
|
||||
const X86Subtarget &Subtarget) {
|
||||
SDLoc dl(N);
|
||||
ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
|
||||
SDValue V1 = SVOp->getOperand(0);
|
||||
SDValue V2 = SVOp->getOperand(1);
|
||||
MVT VT = SVOp->getSimpleValueType(0);
|
||||
unsigned NumElems = VT.getVectorNumElements();
|
||||
|
||||
if (V1.getOpcode() == ISD::CONCAT_VECTORS &&
|
||||
V2.getOpcode() == ISD::CONCAT_VECTORS) {
|
||||
//
|
||||
// 0,0,0,...
|
||||
// |
|
||||
// V UNDEF BUILD_VECTOR UNDEF
|
||||
// \ / \ /
|
||||
// CONCAT_VECTOR CONCAT_VECTOR
|
||||
// \ /
|
||||
// \ /
|
||||
// RESULT: V + zero extended
|
||||
//
|
||||
if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR ||
|
||||
!V2.getOperand(1).isUndef() || !V1.getOperand(1).isUndef())
|
||||
return SDValue();
|
||||
|
||||
if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode()))
|
||||
return SDValue();
|
||||
|
||||
// To match the shuffle mask, the first half of the mask should
|
||||
// be exactly the first vector, and all the rest a splat with the
|
||||
// first element of the second one.
|
||||
for (unsigned i = 0; i != NumElems/2; ++i)
|
||||
if (!isUndefOrEqual(SVOp->getMaskElt(i), i) ||
|
||||
!isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems))
|
||||
return SDValue();
|
||||
|
||||
// If V1 is coming from a vector load then just fold to a VZEXT_LOAD.
|
||||
if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(V1.getOperand(0))) {
|
||||
if (Ld->hasNUsesOfValue(1, 0)) {
|
||||
SDVTList Tys = DAG.getVTList(MVT::v4i64, MVT::Other);
|
||||
SDValue Ops[] = { Ld->getChain(), Ld->getBasePtr() };
|
||||
SDValue ResNode =
|
||||
DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops,
|
||||
Ld->getMemoryVT(),
|
||||
Ld->getPointerInfo(),
|
||||
Ld->getAlignment(),
|
||||
false/*isVolatile*/, true/*ReadMem*/,
|
||||
false/*WriteMem*/);
|
||||
|
||||
// Make sure the newly-created LOAD is in the same position as Ld in
|
||||
// terms of dependency. We create a TokenFactor for Ld and ResNode,
|
||||
// and update uses of Ld's output chain to use the TokenFactor.
|
||||
if (Ld->hasAnyUseOfValue(1)) {
|
||||
SDValue NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
||||
SDValue(Ld, 1), SDValue(ResNode.getNode(), 1));
|
||||
DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), NewChain);
|
||||
DAG.UpdateNodeOperands(NewChain.getNode(), SDValue(Ld, 1),
|
||||
SDValue(ResNode.getNode(), 1));
|
||||
}
|
||||
|
||||
return DAG.getBitcast(VT, ResNode);
|
||||
}
|
||||
}
|
||||
|
||||
// Emit a zeroed vector and insert the desired subvector on its
|
||||
// first half.
|
||||
SDValue Zeros = getZeroVector(VT, Subtarget, DAG, dl);
|
||||
SDValue InsV = insert128BitVector(Zeros, V1.getOperand(0), 0, DAG, dl);
|
||||
return DCI.CombineTo(N, InsV);
|
||||
}
|
||||
|
||||
return SDValue();
|
||||
}
|
||||
|
||||
// Attempt to match a combined shuffle mask against supported unary shuffle
|
||||
// instructions.
|
||||
// TODO: Investigate sharing more of this with shuffle lowering.
|
||||
|
@ -26411,11 +26334,6 @@ static SDValue combineShuffle(SDNode *N, SelectionDAG &DAG,
|
|||
if (SDValue AddSub = combineShuffleToAddSub(N, Subtarget, DAG))
|
||||
return AddSub;
|
||||
|
||||
// Combine 256-bit vector shuffles. This is only profitable when in AVX mode
|
||||
if (TLI.isTypeLegal(VT) && Subtarget.hasFp256() && VT.is256BitVector() &&
|
||||
N->getOpcode() == ISD::VECTOR_SHUFFLE)
|
||||
return combineShuffle256(N, DAG, DCI, Subtarget);
|
||||
|
||||
// During Type Legalization, when promoting illegal vector types,
|
||||
// the backend might introduce new shuffle dag nodes and bitcasts.
|
||||
//
|
||||
|
|
Loading…
Reference in New Issue