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[X86] Stop changing f128 fand/for/fxor to v2i64. 

The additional patterns don't cost us much and it seems better than changing element widths.

llvm-svn: 345564
This commit is contained in:
Craig Topper 2018-10-30 03:27:11 +00:00
parent d8e14a5901
commit 676d7a7a43
2 changed files with 37 additions and 20 deletions
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36
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -37745,27 +37745,27 @@ static SDValue lowerX86FPLogicOp(SDNode *N, SelectionDAG &DAG,
const X86Subtarget &Subtarget) { const X86Subtarget &Subtarget) {
MVT VT = N->getSimpleValueType(0); MVT VT = N->getSimpleValueType(0);
// If we have integer vector types available, use the integer opcodes. // If we have integer vector types available, use the integer opcodes.
if ((VT.isVector() || VT == MVT::f128) && Subtarget.hasSSE2()) { if (!VT.isVector() || !Subtarget.hasSSE2())
SDLoc dl(N); return SDValue();
unsigned IntBits = std::min(VT.getScalarSizeInBits(), 64U); SDLoc dl(N);
MVT IntSVT = MVT::getIntegerVT(IntBits);
MVT IntVT = MVT::getVectorVT(IntSVT, VT.getSizeInBits() / IntBits);
SDValue Op0 = DAG.getBitcast(IntVT, N->getOperand(0)); unsigned IntBits = VT.getScalarSizeInBits();
SDValue Op1 = DAG.getBitcast(IntVT, N->getOperand(1)); MVT IntSVT = MVT::getIntegerVT(IntBits);
unsigned IntOpcode; MVT IntVT = MVT::getVectorVT(IntSVT, VT.getSizeInBits() / IntBits);
switch (N->getOpcode()) {
default: llvm_unreachable("Unexpected FP logic op"); SDValue Op0 = DAG.getBitcast(IntVT, N->getOperand(0));
case X86ISD::FOR: IntOpcode = ISD::OR; break; SDValue Op1 = DAG.getBitcast(IntVT, N->getOperand(1));
case X86ISD::FXOR: IntOpcode = ISD::XOR; break; unsigned IntOpcode;
case X86ISD::FAND: IntOpcode = ISD::AND; break; switch (N->getOpcode()) {
case X86ISD::FANDN: IntOpcode = X86ISD::ANDNP; break; default: llvm_unreachable("Unexpected FP logic op");
} case X86ISD::FOR: IntOpcode = ISD::OR; break;
SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1); case X86ISD::FXOR: IntOpcode = ISD::XOR; break;
return DAG.getBitcast(VT, IntOp); case X86ISD::FAND: IntOpcode = ISD::AND; break;
case X86ISD::FANDN: IntOpcode = X86ISD::ANDNP; break;
} }
return SDValue(); SDValue IntOp = DAG.getNode(IntOpcode, dl, IntVT, Op0, Op1);
return DAG.getBitcast(VT, IntOp);
} }

21
llvm/lib/Target/X86/X86InstrVecCompiler.td
View File

@ -466,8 +466,6 @@ def : Pat<(loadf128 addr:$src),
(VMOVUPSZ128rm addr:$src)>; (VMOVUPSZ128rm addr:$src)>;
} }
// With SSE2 the DAG combiner converts fp logic ops to integer logic ops to
// reduce patterns.
let Predicates = [UseSSE1] in { let Predicates = [UseSSE1] in {
// andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2 // andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2
def : Pat<(f128 (X86fand VR128:$src1, (memopf128 addr:$src2))), def : Pat<(f128 (X86fand VR128:$src1, (memopf128 addr:$src2))),
@ -489,4 +487,23 @@ def : Pat<(f128 (X86fxor VR128:$src1, VR128:$src2)),
(XORPSrr VR128:$src1, VR128:$src2)>; (XORPSrr VR128:$src1, VR128:$src2)>;
} }
let Predicates = [HasAVX] in {
// andps is shorter than andpd or pand. andps is SSE and andpd/pand are in SSE2
def : Pat<(f128 (X86fand VR128:$src1, (loadf128 addr:$src2))),
(VANDPSrm VR128:$src1, f128mem:$src2)>;
def : Pat<(f128 (X86fand VR128:$src1, VR128:$src2)),
(VANDPSrr VR128:$src1, VR128:$src2)>;
def : Pat<(f128 (X86for VR128:$src1, (loadf128 addr:$src2))),
(VORPSrm VR128:$src1, f128mem:$src2)>;
def : Pat<(f128 (X86for VR128:$src1, VR128:$src2)),
(VORPSrr VR128:$src1, VR128:$src2)>;
def : Pat<(f128 (X86fxor VR128:$src1, (loadf128 addr:$src2))),
(VXORPSrm VR128:$src1, f128mem:$src2)>;
def : Pat<(f128 (X86fxor VR128:$src1, VR128:$src2)),
(VXORPSrr VR128:$src1, VR128:$src2)>;
}