forked from OSchip/llvm-project
Add conditional branch instructions and their patterns.
llvm-svn: 166134
This commit is contained in:
Reed Kotler
parent
d228483d8c
commit
6743924a32
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@ -25,7 +25,7 @@
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using namespace llvm;
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Mips16InstrInfo::Mips16InstrInfo(MipsTargetMachine &tm)
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: MipsInstrInfo(tm, /* FIXME: set mips16 unconditional br */ 0),
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: MipsInstrInfo(tm, Mips::BimmX16),
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RI(*tm.getSubtargetImpl()) {}
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const MipsRegisterInfo &Mips16InstrInfo::getRegisterInfo() const {
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@ -137,12 +137,39 @@ bool Mips16InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
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/// GetOppositeBranchOpc - Return the inverse of the specified
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/// opcode, e.g. turning BEQ to BNE.
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unsigned Mips16InstrInfo::GetOppositeBranchOpc(unsigned Opc) const {
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switch (Opc) {
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default: llvm_unreachable("Illegal opcode!");
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case Mips::BeqzRxImmX16: return Mips::BnezRxImmX16;
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case Mips::BnezRxImmX16: return Mips::BeqzRxImmX16;
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case Mips::BteqzT8CmpX16: return Mips::BtnezT8CmpX16;
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case Mips::BteqzT8SltX16: return Mips::BtnezT8SltX16;
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case Mips::BteqzT8SltiX16: return Mips::BtnezT8SltiX16;
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case Mips::BtnezX16: return Mips::BteqzX16;
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case Mips::BtnezT8CmpiX16: return Mips::BteqzT8CmpiX16;
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case Mips::BtnezT8SltuX16: return Mips::BteqzT8SltuX16;
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case Mips::BtnezT8SltiuX16: return Mips::BteqzT8SltiuX16;
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case Mips::BteqzX16: return Mips::BtnezX16;
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case Mips::BteqzT8CmpiX16: return Mips::BtnezT8CmpiX16;
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case Mips::BteqzT8SltuX16: return Mips::BtnezT8SltuX16;
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case Mips::BteqzT8SltiuX16: return Mips::BtnezT8SltiuX16;
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case Mips::BtnezT8CmpX16: return Mips::BteqzT8CmpX16;
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case Mips::BtnezT8SltX16: return Mips::BteqzT8SltX16;
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case Mips::BtnezT8SltiX16: return Mips::BteqzT8SltiX16;
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}
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assert(false && "Implement this function.");
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return 0;
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}
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unsigned Mips16InstrInfo::GetAnalyzableBrOpc(unsigned Opc) const {
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return 0;
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return (Opc == Mips::BeqzRxImmX16 || Opc == Mips::BimmX16 ||
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Opc == Mips::BnezRxImmX16 || Opc == Mips::BteqzX16 ||
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Opc == Mips::BteqzT8CmpX16 || Opc == Mips::BteqzT8CmpiX16 ||
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Opc == Mips::BteqzT8SltX16 || Opc == Mips::BteqzT8SltuX16 ||
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Opc == Mips::BteqzT8SltiX16 || Opc == Mips::BteqzT8SltiuX16 ||
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Opc == Mips::BtnezX16 || Opc == Mips::BtnezT8CmpX16 ||
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Opc == Mips::BtnezT8CmpiX16 || Opc == Mips::BtnezT8SltX16 ||
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Opc == Mips::BtnezT8SltuX16 || Opc == Mips::BtnezT8SltiX16 ||
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Opc == Mips::BtnezT8SltiuX16 ) ? Opc : 0;
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}
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void Mips16InstrInfo::ExpandRetRA16(MachineBasicBlock &MBB,
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@ -20,6 +20,26 @@ def mem16 : Operand<i32> {
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let EncoderMethod = "getMemEncoding";
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}
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//
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// EXT-I instruction format
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//
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class FEXT_I16_ins<bits<5> eop, string asmstr, InstrItinClass itin> :
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FEXT_I16<eop, (outs), (ins brtarget:$imm16),
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!strconcat(asmstr, "\t$imm16"),[], itin>;
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//
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// EXT-I8 instruction format
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//
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class FEXT_I816_ins_base<bits<3> _func, string asmstr,
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string asmstr2, InstrItinClass itin>:
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FEXT_I816<_func, (outs), (ins uimm16:$imm), !strconcat(asmstr, asmstr2),
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[], itin>;
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class FEXT_I816_ins<bits<3> _func, string asmstr,
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InstrItinClass itin>:
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FEXT_I816_ins_base<_func, asmstr, "\t$imm", itin>;
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//
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// Assembler formats in alphabetical order.
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// Natural and pseudos are mixed together.
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@ -40,6 +60,11 @@ class FEXT_RI16_ins<bits<5> _op, string asmstr,
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class FEXT_RI16_PC_ins<bits<5> _op, string asmstr, InstrItinClass itin>:
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FEXT_RI16_ins_base<_op, asmstr, "\t$rx, $$pc, $imm", itin>;
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class FEXT_RI16_B_ins<bits<5> _op, string asmstr,
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InstrItinClass itin>:
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FEXT_RI16<_op, (outs), (ins CPU16Regs:$rx, brtarget:$imm),
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!strconcat(asmstr, "\t$rx, $imm"), [], itin>;
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class FEXT_2RI16_ins<bits<5> _op, string asmstr,
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InstrItinClass itin>:
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FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
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@ -47,6 +72,7 @@ class FEXT_2RI16_ins<bits<5> _op, string asmstr,
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let Constraints = "$rx_ = $rx";
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}
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// this has an explicit sp argument that we ignore to work around a problem
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// in the compiler
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class FEXT_RI16_SP_explicit_ins<bits<5> _op, string asmstr,
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@ -75,6 +101,31 @@ class FEXT_SHIFT16_ins<bits<2> _f, string asmstr, InstrItinClass itin>:
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FEXT_SHIFT16<_f, (outs CPU16Regs:$rx), (ins CPU16Regs:$ry, shamt:$sa),
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!strconcat(asmstr, "\t$rx, $ry, $sa"), [], itin>;
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//
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// EXT-T8I8
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//
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class FEXT_T8I816_ins<bits<3> _func, string asmstr, string asmstr2,
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InstrItinClass itin>:
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FEXT_I816<_func, (outs),
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(ins CPU16Regs:$rx, CPU16Regs:$ry, brtarget:$imm),
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!strconcat(asmstr2, !strconcat("\t$rx, $ry\n\t",
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!strconcat(asmstr, "\t$imm"))),[], itin> {
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let isCodeGenOnly=1;
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}
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//
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// EXT-T8I8I
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//
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class FEXT_T8I8I16_ins<bits<3> _func, string asmstr, string asmstr2,
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InstrItinClass itin>:
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FEXT_I816<_func, (outs),
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(ins CPU16Regs:$rx, simm16:$imm, brtarget:$targ),
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!strconcat(asmstr2, !strconcat("\t$rx, $imm\n\t",
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!strconcat(asmstr, "\t$targ"))), [], itin> {
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let isCodeGenOnly=1;
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}
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//
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//
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// I8_MOVR32 instruction format (used only by the MOVR32 instructio
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@ -165,6 +216,17 @@ class ArithLogic16Defs<bit isCom=0> {
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bit neverHasSideEffects = 1;
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}
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class branch16 {
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bit isBranch = 1;
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bit isTerminator = 1;
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bit isBarrier = 1;
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}
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class cbranch16 {
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bit isBranch = 1;
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bit isTerminator = 1;
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}
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class MayLoad {
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bit mayLoad = 1;
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}
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@ -204,6 +266,69 @@ def AdduRxRyRz16: FRRR16_ins<01, "addu", IIAlu>, ArithLogic16Defs<1>;
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// To do a bitwise logical AND.
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def AndRxRxRy16: FRxRxRy16_ins<0b01100, "and", IIAlu>, ArithLogic16Defs<1>;
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//
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// Format: BEQZ rx, offset MIPS16e
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// Purpose: Branch on Equal to Zero (Extended)
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// To test a GPR then do a PC-relative conditional branch.
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//
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def BeqzRxImmX16: FEXT_RI16_B_ins<0b00100, "beqz", IIAlu>, cbranch16;
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// Format: B offset MIPS16e
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// Purpose: Unconditional Branch
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// To do an unconditional PC-relative branch.
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//
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def BimmX16: FEXT_I16_ins<0b00010, "b", IIAlu>, branch16;
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//
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// Format: BNEZ rx, offset MIPS16e
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// Purpose: Branch on Not Equal to Zero (Extended)
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// To test a GPR then do a PC-relative conditional branch.
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//
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def BnezRxImmX16: FEXT_RI16_B_ins<0b00101, "bnez", IIAlu>, cbranch16;
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//
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// Format: BTEQZ offset MIPS16e
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// Purpose: Branch on T Equal to Zero (Extended)
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// To test special register T then do a PC-relative conditional branch.
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//
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def BteqzX16: FEXT_I816_ins<0b000, "bteqz", IIAlu>, cbranch16;
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def BteqzT8CmpX16: FEXT_T8I816_ins<0b000, "bteqz", "cmp", IIAlu>, cbranch16;
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def BteqzT8CmpiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "cmpi", IIAlu>,
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cbranch16;
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def BteqzT8SltX16: FEXT_T8I816_ins<0b000, "bteqz", "slt", IIAlu>, cbranch16;
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def BteqzT8SltuX16: FEXT_T8I816_ins<0b000, "bteqz", "sltu", IIAlu>, cbranch16;
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def BteqzT8SltiX16: FEXT_T8I8I16_ins<0b000, "bteqz", "slti", IIAlu>, cbranch16;
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def BteqzT8SltiuX16: FEXT_T8I8I16_ins<0b000, "bteqz", "sltiu", IIAlu>,
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cbranch16;
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//
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// Format: BTNEZ offset MIPS16e
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// Purpose: Branch on T Not Equal to Zero (Extended)
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// To test special register T then do a PC-relative conditional branch.
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//
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def BtnezX16: FEXT_I816_ins<0b001, "btnez", IIAlu> ,cbranch16;
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def BtnezT8CmpX16: FEXT_T8I816_ins<0b000, "btnez", "cmp", IIAlu>, cbranch16;
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def BtnezT8CmpiX16: FEXT_T8I8I16_ins<0b000, "btnez", "cmpi", IIAlu>, cbranch16;
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def BtnezT8SltX16: FEXT_T8I816_ins<0b000, "btnez", "slt", IIAlu>, cbranch16;
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def BtnezT8SltuX16: FEXT_T8I816_ins<0b000, "btnez", "sltu", IIAlu>, cbranch16;
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def BtnezT8SltiX16: FEXT_T8I8I16_ins<0b000, "btnez", "slti", IIAlu>, cbranch16;
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def BtnezT8SltiuX16: FEXT_T8I8I16_ins<0b000, "btnez", "sltiu", IIAlu>,
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cbranch16;
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//
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// Format: DIV rx, ry MIPS16e
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// Purpose: Divide Word
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@ -562,6 +687,11 @@ def: StoreM16_pat<truncstorei8, SbRxRyOffMemX16>;
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def: StoreM16_pat<truncstorei16, ShRxRyOffMemX16>;
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def: StoreM16_pat<store, SwRxRyOffMemX16>;
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// Unconditional branch
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class UncondBranch16_pat<SDNode OpNode, Instruction I>:
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Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> {
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let Predicates = [RelocPIC, InMips16Mode];
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}
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// Jump and Link (Call)
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let isCall=1, hasDelaySlot=1 in
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@ -574,7 +704,144 @@ let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1,
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hasExtraSrcRegAllocReq = 1 in
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def RetRA16 : MipsPseudo16<(outs), (ins), "", [(MipsRet)]>;
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//
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// Some branch conditional patterns are not generated by llvm at this time.
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// Some are for seemingly arbitrary reasons not used: i.e. with signed number
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// comparison they are used and for unsigned a different pattern is used.
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// I am pushing upstream from the full mips16 port and it seemed that I needed
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// these earlier and the mips32 port has these but now I cannot create test
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// cases that use these patterns. While I sort this all out I will leave these
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// extra patterns commented out and if I can be sure they are really not used,
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// I will delete the code. I don't want to check the code in uncommented without
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// a valid test case. In some cases, the compiler is generating patterns with
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// setcc instead and earlier I had implemented setcc first so may have masked
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// the problem. The setcc variants are suboptimal for mips16 so I may wantto
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// figure out how to enable the brcond patterns or else possibly new
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// combinations of of brcond and setcc.
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//
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//
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// bcond-seteq
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//
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def: Mips16Pat
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<(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
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(BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
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>;
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def: Mips16Pat
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<(brcond (i32 (seteq CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
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(BteqzT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
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>;
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def: Mips16Pat
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<(brcond (i32 (seteq CPU16Regs:$rx, 0)), bb:$targ16),
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(BeqzRxImmX16 CPU16Regs:$rx, bb:$targ16)
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>;
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//
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// bcond-setgt (do we need to have this pair of setlt, setgt??)
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//
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def: Mips16Pat
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<(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
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(BtnezT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
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>;
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//
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// bcond-setge
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//
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def: Mips16Pat
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<(brcond (i32 (setge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
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(BteqzT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
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>;
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//
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// never called because compiler transforms a >= k to a > (k-1)
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//def: Mips16Pat
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// <(brcond (i32 (setge CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
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// (BteqzT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
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// >;
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//
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// bcond-setlt
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//
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def: Mips16Pat
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<(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
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(BtnezT8SltX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
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>;
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def: Mips16Pat
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<(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16),
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(BtnezT8SltiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$imm16)
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>;
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//
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// bcond-setle
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//
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def: Mips16Pat
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<(brcond (i32 (setle CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
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(BteqzT8SltX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
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>;
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//
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// bcond-setne
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//
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def: Mips16Pat
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<(brcond (i32 (setne CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
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(BtnezT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
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>;
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def: Mips16Pat
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<(brcond (i32 (setne CPU16Regs:$rx, immZExt16:$imm)), bb:$targ16),
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(BtnezT8CmpiX16 CPU16Regs:$rx, immSExt16:$imm, bb:$targ16)
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>;
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def: Mips16Pat
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<(brcond (i32 (setne CPU16Regs:$rx, 0)), bb:$targ16),
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(BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
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>;
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//
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// This needs to be there but I forget which code will generate it
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//
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def: Mips16Pat
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<(brcond CPU16Regs:$rx, bb:$targ16),
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(BnezRxImmX16 CPU16Regs:$rx, bb:$targ16)
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>;
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//
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//
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// bcond-setugt
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//
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//def: Mips16Pat
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// <(brcond (i32 (setugt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
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// (BtnezT8SltuX16 CPU16Regs:$ry, CPU16Regs:$rx, bb:$imm16)
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// >;
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//
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// bcond-setuge
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//
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//def: Mips16Pat
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// <(brcond (i32 (setuge CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
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// (BteqzT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
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// >;
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//
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// bcond-setult
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//
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//def: Mips16Pat
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// <(brcond (i32 (setult CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16),
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// (BtnezT8SltuX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16)
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// >;
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def: UncondBranch16_pat<br, BimmX16>;
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// Small immediates
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def: Mips16Pat<(i32 immSExt16:$in),
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(AddiuRxRxImmX16 (Move32R16 ZERO), immSExt16:$in)>;
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def: Mips16Pat<(i32 immZExt16:$in), (LiRxImmX16 immZExt16:$in)>;
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//
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@ -0,0 +1,38 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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|
||||
@i = global i32 5, align 4
|
||||
@j = global i32 10, align 4
|
||||
@result = global i32 0, align 4
|
||||
|
||||
define void @test() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @i, align 4
|
||||
%1 = load i32* @j, align 4
|
||||
%cmp = icmp eq i32 %0, %1
|
||||
; 16: cmp ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: bteqz $[[LABEL:[0-9A-Ba-b_]+]]
|
||||
; 16: $[[LABEL]]:
|
||||
br i1 %cmp, label %if.end, label %if.then
|
||||
|
||||
if.then: ; preds = %entry
|
||||
store i32 1, i32* @result, align 4
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %entry, %if.then
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
|
||||
@i = global i32 5, align 4
|
||||
@result = global i32 0, align 4
|
||||
|
||||
define void @test() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @i, align 4
|
||||
%cmp = icmp eq i32 %0, 10
|
||||
br i1 %cmp, label %if.end, label %if.then
|
||||
; 16: cmpi ${{[0-9]+}}, {{[0-9]+}}
|
||||
; 16: bteqz $[[LABEL:[0-9A-Ba-b_]+]]
|
||||
; 16: $[[LABEL]]:
|
||||
if.then: ; preds = %entry
|
||||
store i32 1, i32* @result, align 4
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %entry, %if.then
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,20 @@
|
|||
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
|
||||
@i = global i32 5, align 4
|
||||
@result = global i32 0, align 4
|
||||
|
||||
define void @test() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @i, align 4
|
||||
%cmp = icmp eq i32 %0, 0
|
||||
br i1 %cmp, label %if.end, label %if.then
|
||||
; 16: beqz ${{[0-9]+}}, $[[LABEL:[0-9A-Ba-b_]+]]
|
||||
; 16: $[[LABEL]]:
|
||||
if.then: ; preds = %entry
|
||||
store i32 1, i32* @result, align 4
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %entry, %if.then
|
||||
ret void
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
|
||||
@i = global i32 5, align 4
|
||||
@j = global i32 10, align 4
|
||||
@k = global i32 5, align 4
|
||||
@result1 = global i32 0, align 4
|
||||
@result2 = global i32 1, align 4
|
||||
|
||||
define void @test() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @i, align 4
|
||||
%1 = load i32* @j, align 4
|
||||
%cmp = icmp slt i32 %0, %1
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: bteqz $[[LABEL:[0-9A-Ba-b_]+]]
|
||||
; 16: $[[LABEL]]:
|
||||
|
||||
if.then: ; preds = %entry
|
||||
store i32 1, i32* @result1, align 4
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %entry
|
||||
%2 = load i32* @k, align 4
|
||||
%cmp1 = icmp slt i32 %0, %2
|
||||
br i1 %cmp1, label %if.then2, label %if.end3
|
||||
|
||||
if.then2: ; preds = %if.end
|
||||
store i32 1, i32* @result1, align 4
|
||||
br label %if.end3
|
||||
|
||||
if.end3: ; preds = %if.then2, %if.end
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
|
||||
@i = global i32 5, align 4
|
||||
@j = global i32 10, align 4
|
||||
@k = global i32 5, align 4
|
||||
@result = global i32 0, align 4
|
||||
|
||||
define void @test() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @i, align 4
|
||||
%1 = load i32* @j, align 4
|
||||
%cmp = icmp sgt i32 %0, %1
|
||||
br i1 %cmp, label %if.end, label %if.then
|
||||
; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: btnez $[[LABEL:[0-9A-Ba-b_]+]]
|
||||
; 16: $[[LABEL]]:
|
||||
if.then: ; preds = %entry
|
||||
store i32 1, i32* @result, align 4
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %entry, %if.then
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
|
||||
@i = global i32 -5, align 4
|
||||
@j = global i32 10, align 4
|
||||
@k = global i32 -5, align 4
|
||||
@result1 = global i32 0, align 4
|
||||
@result2 = global i32 1, align 4
|
||||
|
||||
define void @test() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @j, align 4
|
||||
%1 = load i32* @i, align 4
|
||||
%cmp = icmp sgt i32 %0, %1
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: bteqz $[[LABEL:[0-9A-Ba-b_]+]]
|
||||
; 16: $[[LABEL]]:
|
||||
|
||||
if.then: ; preds = %entry
|
||||
store i32 1, i32* @result1, align 4
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %entry
|
||||
%2 = load i32* @k, align 4
|
||||
%cmp1 = icmp sgt i32 %1, %2
|
||||
br i1 %cmp1, label %if.then2, label %if.end3
|
||||
|
||||
if.then2: ; preds = %if.end
|
||||
store i32 0, i32* @result1, align 4
|
||||
br label %if.end3
|
||||
|
||||
if.end3: ; preds = %if.then2, %if.end
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
|
||||
@i = global i32 5, align 4
|
||||
@j = global i32 10, align 4
|
||||
@k = global i32 5, align 4
|
||||
@result = global i32 0, align 4
|
||||
|
||||
define void @test() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @j, align 4
|
||||
%1 = load i32* @i, align 4
|
||||
%cmp = icmp slt i32 %0, %1
|
||||
br i1 %cmp, label %if.end, label %if.then
|
||||
|
||||
; 16: slt ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: btnez $[[LABEL:[0-9A-Ba-b_]+]]
|
||||
; 16: $[[LABEL]]:
|
||||
|
||||
if.then: ; preds = %entry
|
||||
store i32 1, i32* @result, align 4
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %entry, %if.then
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,26 @@
|
|||
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
|
||||
@i = global i32 5, align 4
|
||||
@j = global i32 5, align 4
|
||||
@result = global i32 0, align 4
|
||||
|
||||
define void @test() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @j, align 4
|
||||
%1 = load i32* @i, align 4
|
||||
%cmp = icmp eq i32 %0, %1
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
; 16: cmp ${{[0-9]+}}, ${{[0-9]+}}
|
||||
; 16: btnez $[[LABEL:[0-9A-Ba-b_]+]]
|
||||
; 16: lw ${{[0-9]+}}, %got(result)(${{[0-9]+}})
|
||||
; 16: $[[LABEL]]:
|
||||
|
||||
if.then: ; preds = %entry
|
||||
store i32 1, i32* @result, align 4
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
|
||||
@j = global i32 5, align 4
|
||||
@result = global i32 0, align 4
|
||||
|
||||
define void @test() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @j, align 4
|
||||
%cmp = icmp eq i32 %0, 5
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
; 16: cmpi ${{[0-9]+}}, {{[0-9]+}}
|
||||
; 16: btnez $[[LABEL:[0-9A-Ba-b_]+]]
|
||||
; 16: lw ${{[0-9]+}}, %got(result)(${{[0-9]+}})
|
||||
; 16: $[[LABEL]]:
|
||||
|
||||
if.then: ; preds = %entry
|
||||
store i32 1, i32* @result, align 4
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
|
||||
|
||||
@j = global i32 0, align 4
|
||||
@result = global i32 0, align 4
|
||||
|
||||
define void @test() nounwind {
|
||||
entry:
|
||||
%0 = load i32* @j, align 4
|
||||
%cmp = icmp eq i32 %0, 0
|
||||
br i1 %cmp, label %if.then, label %if.end
|
||||
|
||||
; 16: bnez ${{[0-9]+}}, $[[LABEL:[0-9A-Ba-b_]+]]
|
||||
; 16: lw ${{[0-9]+}}, %got(result)(${{[0-9]+}})
|
||||
; 16: $[[LABEL]]:
|
||||
|
||||
if.then: ; preds = %entry
|
||||
store i32 1, i32* @result, align 4
|
||||
br label %if.end
|
||||
|
||||
if.end: ; preds = %if.then, %entry
|
||||
ret void
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue