forked from OSchip/llvm-project
parent
04196acdcb
commit
6732dcd5b3
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@ -47,8 +47,8 @@ let Namespace = "X86" in {
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def AL : RegisterGroup<"AL", [AX,EAX]>, DwarfRegNum<0>;
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def CL : RegisterGroup<"CL", [CX,ECX]>, DwarfRegNum<2>;
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def DL : RegisterGroup<"DL", [DX,EDX]>, DwarfRegNum<1>;
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def BL : RegisterGroup<"BL", [BX,EBX]>, DwarfRegNum<0>;
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def AH : RegisterGroup<"AH", [AX,EAX]>, DwarfRegNum<2>;
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def BL : RegisterGroup<"BL", [BX,EBX]>, DwarfRegNum<3>;
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def AH : RegisterGroup<"AH", [AX,EAX]>, DwarfRegNum<0>;
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def CH : RegisterGroup<"CH", [CX,ECX]>, DwarfRegNum<2>;
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def DH : RegisterGroup<"DH", [DX,EDX]>, DwarfRegNum<1>;
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def BH : RegisterGroup<"BH", [BX,EBX]>, DwarfRegNum<3>;
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