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[X86][SSE] Add UNDEF handling to combineSelect ISD::USUBSAT matching (PR40083) 

llvm-svn: 352330
This commit is contained in:
Simon Pilgrim 2019-01-27 21:01:23 +00:00
parent e5cf884018
commit 670a6971f8
2 changed files with 14 additions and 35 deletions
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12
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -34520,14 +34520,16 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
// If the RHS is a constant we have to reverse the const // If the RHS is a constant we have to reverse the const
// canonicalization. // canonicalization.
// x > C-1 ? x+-C : 0 --> subus x, C // x > C-1 ? x+-C : 0 --> subus x, C
// TODO: Handle build_vectors with undef elements.
auto MatchUSUBSAT = [](ConstantSDNode *Op, ConstantSDNode *Cond) { auto MatchUSUBSAT = [](ConstantSDNode *Op, ConstantSDNode *Cond) {
return Cond->getAPIntValue() == (-Op->getAPIntValue() - 1); return (!Op && !Cond) ||
(Op && Cond &&
Cond->getAPIntValue() == (-Op->getAPIntValue() - 1));
}; };
if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD && if (CC == ISD::SETUGT && Other->getOpcode() == ISD::ADD &&
ISD::matchBinaryPredicate(OpRHS, CondRHS, MatchUSUBSAT)) { ISD::matchBinaryPredicate(OpRHS, CondRHS, MatchUSUBSAT,
OpRHS = DAG.getNode(ISD::SUB, DL, VT, /*AllowUndefs*/ true)) {
DAG.getConstant(0, DL, VT), OpRHS); OpRHS = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
OpRHS);
return DAG.getNode(ISD::USUBSAT, DL, VT, OpLHS, OpRHS); return DAG.getNode(ISD::USUBSAT, DL, VT, OpLHS, OpRHS);
} }

37
llvm/test/CodeGen/X86/psubus.ll
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@ -2752,38 +2752,15 @@ entry:
define i64 @test31(<2 x i64> %x) { define i64 @test31(<2 x i64> %x) {
; SSE-LABEL: test31: ; SSE-LABEL: test31:
; SSE: # %bb.0: ; SSE: # %bb.0:
; SSE-NEXT: movdqa {{.*#+}} xmm1 = <70,70,70,70,70,70,70,70,u,u,u,u,u,u,u,u> ; SSE-NEXT: psubusb {{.*}}(%rip), %xmm0
; SSE-NEXT: pminub %xmm0, %xmm1 ; SSE-NEXT: movq %xmm0, %rax
; SSE-NEXT: pcmpeqb %xmm0, %xmm1
; SSE-NEXT: paddb {{.*}}(%rip), %xmm0
; SSE-NEXT: pandn %xmm0, %xmm1
; SSE-NEXT: movq %xmm1, %rax
; SSE-NEXT: retq ; SSE-NEXT: retq
; ;
; AVX1-LABEL: test31: ; AVX-LABEL: test31:
; AVX1: # %bb.0: ; AVX: # %bb.0:
; AVX1-NEXT: vpminub {{.*}}(%rip), %xmm0, %xmm1 ; AVX-NEXT: vpsubusb {{.*}}(%rip), %xmm0, %xmm0
; AVX1-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm1 ; AVX-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0 ; AVX-NEXT: retq
; AVX1-NEXT: vpandn %xmm0, %xmm1, %xmm0
; AVX1-NEXT: vmovq %xmm0, %rax
; AVX1-NEXT: retq
;
; AVX2-LABEL: test31:
; AVX2: # %bb.0:
; AVX2-NEXT: vpminub {{.*}}(%rip), %xmm0, %xmm1
; AVX2-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm1
; AVX2-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0
; AVX2-NEXT: vpandn %xmm0, %xmm1, %xmm0
; AVX2-NEXT: vmovq %xmm0, %rax
; AVX2-NEXT: retq
;
; AVX512-LABEL: test31:
; AVX512: # %bb.0:
; AVX512-NEXT: vpcmpnleub {{.*}}(%rip), %xmm0, %k1
; AVX512-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0 {%k1} {z}
; AVX512-NEXT: vmovq %xmm0, %rax
; AVX512-NEXT: retq
%t0 = bitcast <2 x i64> %x to <16 x i8> %t0 = bitcast <2 x i64> %x to <16 x i8>
%cmp = icmp ugt <16 x i8> %t0, <i8 70, i8 70, i8 70, i8 70, i8 70, i8 70, i8 70, i8 70, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef> %cmp = icmp ugt <16 x i8> %t0, <i8 70, i8 70, i8 70, i8 70, i8 70, i8 70, i8 70, i8 70, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>
%bop = add <16 x i8> %t0, <i8 -71, i8 -71, i8 -71, i8 -71, i8 -71, i8 -71, i8 -71, i8 -71, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef> %bop = add <16 x i8> %t0, <i8 -71, i8 -71, i8 -71, i8 -71, i8 -71, i8 -71, i8 -71, i8 -71, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef, i8 undef>