maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

AMDGPU/GlobalISel: Clean-up code around ISel for Intrinsics. 

Summary:
A minor code clean-up around ISel for intrinsic llvm.amdgcn.end.cf()

Reviewers: arsenm, mshivama

Reviewed By: arsenm

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D73358
This commit is contained in:
Maheaha Shivamallappa 2020-01-26 13:31:53 +05:30 committed by cdevadas
parent 70389be7a0
commit 66f93071cd
2 changed files with 18 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
View File

@ -1027,6 +1027,21 @@ AMDGPUInstructionSelector::splitBufferOffsets(MachineIRBuilder &B,
return std::make_tuple(BaseReg, ImmOffset, TotalConstOffset); return std::make_tuple(BaseReg, ImmOffset, TotalConstOffset);
} }
bool AMDGPUInstructionSelector::selectEndCfIntrinsic(MachineInstr &MI) const {
// FIXME: Manually selecting to avoid dealiing with the SReg_1 trick
// SelectionDAG uses for wave32 vs wave64.
MachineBasicBlock *BB = MI.getParent();
BuildMI(*BB, &MI, MI.getDebugLoc(), TII.get(AMDGPU::SI_END_CF))
.add(MI.getOperand(1));
Register Reg = MI.getOperand(1).getReg();
MI.eraseFromParent();
if (!MRI->getRegClassOrNull(Reg))
MRI->setRegClass(Reg, TRI.getWaveMaskRegClass());
return true;
}
bool AMDGPUInstructionSelector::selectStoreIntrinsic(MachineInstr &MI, bool AMDGPUInstructionSelector::selectStoreIntrinsic(MachineInstr &MI,
bool IsFormat) const { bool IsFormat) const {
MachineIRBuilder B(MI); MachineIRBuilder B(MI);
@ -1306,23 +1321,10 @@ bool AMDGPUInstructionSelector::selectDSAppendConsume(MachineInstr &MI,
bool AMDGPUInstructionSelector::selectG_INTRINSIC_W_SIDE_EFFECTS( bool AMDGPUInstructionSelector::selectG_INTRINSIC_W_SIDE_EFFECTS(
MachineInstr &I) const { MachineInstr &I) const {
MachineBasicBlock *BB = I.getParent();
unsigned IntrinsicID = I.getIntrinsicID(); unsigned IntrinsicID = I.getIntrinsicID();
switch (IntrinsicID) { switch (IntrinsicID) {
case Intrinsic::amdgcn_end_cf: { case Intrinsic::amdgcn_end_cf:
// FIXME: Manually selecting to avoid dealiing with the SReg_1 trick return selectEndCfIntrinsic(I);
// SelectionDAG uses for wave32 vs wave64.
BuildMI(*BB, &I, I.getDebugLoc(),
TII.get(AMDGPU::SI_END_CF))
.add(I.getOperand(1));
Register Reg = I.getOperand(1).getReg();
I.eraseFromParent();
if (!MRI->getRegClassOrNull(Reg))
MRI->setRegClass(Reg, TRI.getWaveMaskRegClass());
return true;
}
case Intrinsic::amdgcn_raw_buffer_store: case Intrinsic::amdgcn_raw_buffer_store:
return selectStoreIntrinsic(I, false); return selectStoreIntrinsic(I, false);
case Intrinsic::amdgcn_raw_buffer_store_format: case Intrinsic::amdgcn_raw_buffer_store_format:

1
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
View File

@ -103,6 +103,7 @@ private:
std::tuple<Register, unsigned, unsigned> std::tuple<Register, unsigned, unsigned>
splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const; splitBufferOffsets(MachineIRBuilder &B, Register OrigOffset) const;
bool selectEndCfIntrinsic(MachineInstr &MI) const;
bool selectStoreIntrinsic(MachineInstr &MI, bool IsFormat) const; bool selectStoreIntrinsic(MachineInstr &MI, bool IsFormat) const;
bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const; bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const; bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;