forked from OSchip/llvm-project
[DAGCombiner] Transform (zext (select c, load1, load2)) -> (select c, zextload1, zextload2)
If extload is legal, following transform
(zext (select c, load1, load2)) -> (select c, zextload1, zextload2)
can save one ext instruction.
Differential Revision: https://reviews.llvm.org/D95086
This commit is contained in:
Guozhi Wei
parent
ea2ff54ccc
commit
66f2d09ebf
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@ -10029,6 +10029,77 @@ SDValue DAGCombiner::visitSETCCCARRY(SDNode *N) {
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return SDValue();
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}
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/// Check if N satisfies:
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/// N is used once.
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/// N is a Load.
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/// The load is compatible with ExtOpcode. It means
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/// If load has explicit zero/sign extension, ExpOpcode must have the same
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/// extension.
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/// Otherwise returns true.
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static bool isCompatibleLoad(SDValue N, unsigned ExtOpcode) {
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if (!N.hasOneUse())
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return false;
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if (!isa<LoadSDNode>(N))
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return false;
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LoadSDNode *Load = cast<LoadSDNode>(N);
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ISD::LoadExtType LoadExt = Load->getExtensionType();
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if (LoadExt == ISD::NON_EXTLOAD || LoadExt == ISD::EXTLOAD)
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return true;
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// Now LoadExt is either SEXTLOAD or ZEXTLOAD, ExtOpcode must have the same
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// extension.
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if ((LoadExt == ISD::SEXTLOAD && ExtOpcode != ISD::SIGN_EXTEND) ||
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(LoadExt == ISD::ZEXTLOAD && ExtOpcode != ISD::ZERO_EXTEND))
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return false;
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return true;
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}
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/// Fold
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/// (sext (select c, load x, load y)) -> (select c, sextload x, sextload y)
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/// (zext (select c, load x, load y)) -> (select c, zextload x, zextload y)
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/// (aext (select c, load x, load y)) -> (select c, extload x, extload y)
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/// This function is called by the DAGCombiner when visiting sext/zext/aext
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/// dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND).
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static SDValue tryToFoldExtendSelectLoad(SDNode *N, const TargetLowering &TLI,
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SelectionDAG &DAG) {
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unsigned Opcode = N->getOpcode();
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SDValue N0 = N->getOperand(0);
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EVT VT = N->getValueType(0);
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SDLoc DL(N);
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assert((Opcode == ISD::SIGN_EXTEND || Opcode == ISD::ZERO_EXTEND ||
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Opcode == ISD::ANY_EXTEND) &&
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"Expected EXTEND dag node in input!");
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if (!(N0->getOpcode() == ISD::SELECT || N0->getOpcode() == ISD::VSELECT) ||
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!N0.hasOneUse())
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return SDValue();
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SDValue Op1 = N0->getOperand(1);
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SDValue Op2 = N0->getOperand(2);
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if (!isCompatibleLoad(Op1, Opcode) || !isCompatibleLoad(Op2, Opcode))
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return SDValue();
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auto ExtLoadOpcode = ISD::EXTLOAD;
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if (Opcode == ISD::SIGN_EXTEND)
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ExtLoadOpcode = ISD::SEXTLOAD;
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else if (Opcode == ISD::ZERO_EXTEND)
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ExtLoadOpcode = ISD::ZEXTLOAD;
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LoadSDNode *Load1 = cast<LoadSDNode>(Op1);
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LoadSDNode *Load2 = cast<LoadSDNode>(Op2);
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if (!TLI.isLoadExtLegal(ExtLoadOpcode, VT, Load1->getMemoryVT()) ||
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!TLI.isLoadExtLegal(ExtLoadOpcode, VT, Load2->getMemoryVT()))
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return SDValue();
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SDValue Ext1 = DAG.getNode(Opcode, DL, VT, Op1);
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SDValue Ext2 = DAG.getNode(Opcode, DL, VT, Op2);
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return DAG.getSelect(DL, VT, N0->getOperand(0), Ext1, Ext2);
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}
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/// Try to fold a sext/zext/aext dag node into a ConstantSDNode or
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/// a build_vector of constants.
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/// This function is called by the DAGCombiner when visiting sext/zext/aext
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@ -10813,6 +10884,9 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
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return DAG.getNode(ISD::ADD, DL, VT, Zext, DAG.getAllOnesConstant(DL, VT));
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}
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if (SDValue Res = tryToFoldExtendSelectLoad(N, TLI, DAG))
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return Res;
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return SDValue();
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}
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@ -11125,6 +11199,9 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
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if (SDValue NewCtPop = widenCtPop(N, DAG))
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return NewCtPop;
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if (SDValue Res = tryToFoldExtendSelectLoad(N, TLI, DAG))
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return Res;
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return SDValue();
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}
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@ -11277,6 +11354,9 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
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if (SDValue NewCtPop = widenCtPop(N, DAG))
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return NewCtPop;
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if (SDValue Res = tryToFoldExtendSelectLoad(N, TLI, DAG))
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return Res;
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return SDValue();
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}
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@ -1,15 +1,14 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s
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; TODO: (zext(select c, load1, load2)) -> (select c, zextload1, zextload2)
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; (zext(select c, load1, load2)) -> (select c, zextload1, zextload2)
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define i64 @zext_scalar(i8* %p, i1 zeroext %c) {
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; CHECK-LABEL: zext_scalar:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzbl (%rdi), %eax
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; CHECK-NEXT: movzbl 1(%rdi), %ecx
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; CHECK-NEXT: movzbl (%rdi), %ecx
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; CHECK-NEXT: movzbl 1(%rdi), %eax
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; CHECK-NEXT: testl %esi, %esi
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; CHECK-NEXT: cmovel %eax, %ecx
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; CHECK-NEXT: movzbl %cl, %eax
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; CHECK-NEXT: cmoveq %rcx, %rax
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; CHECK-NEXT: retq
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%ld1 = load volatile i8, i8* %p
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%arrayidx1 = getelementptr inbounds i8, i8* %p, i64 1
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@ -22,13 +21,10 @@ define i64 @zext_scalar(i8* %p, i1 zeroext %c) {
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define i64 @zext_scalar2(i8* %p, i16* %q, i1 zeroext %c) {
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; CHECK-LABEL: zext_scalar2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzbl (%rdi), %eax
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; CHECK-NEXT: testl %edx, %edx
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; CHECK-NEXT: je .LBB1_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: movzbl (%rdi), %ecx
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; CHECK-NEXT: movzwl (%rsi), %eax
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; CHECK-NEXT: .LBB1_2:
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; CHECK-NEXT: movzwl %ax, %eax
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; CHECK-NEXT: testl %edx, %edx
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; CHECK-NEXT: cmoveq %rcx, %rax
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; CHECK-NEXT: retq
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%ld1 = load volatile i8, i8* %p
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%ext_ld1 = zext i8 %ld1 to i16
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@ -58,15 +54,14 @@ define i64 @zext_scalar_neg(i8* %p, i16* %q, i1 zeroext %c) {
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ret i64 %cond
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}
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; TODO: (sext(select c, load1, load2)) -> (select c, sextload1, sextload2)
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; (sext(select c, load1, load2)) -> (select c, sextload1, sextload2)
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define i64 @sext_scalar(i8* %p, i1 zeroext %c) {
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; CHECK-LABEL: sext_scalar:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movzbl (%rdi), %eax
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; CHECK-NEXT: movzbl 1(%rdi), %ecx
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; CHECK-NEXT: movsbq (%rdi), %rcx
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; CHECK-NEXT: movsbq 1(%rdi), %rax
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; CHECK-NEXT: testl %esi, %esi
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; CHECK-NEXT: cmovel %eax, %ecx
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; CHECK-NEXT: movsbq %cl, %rax
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; CHECK-NEXT: cmoveq %rcx, %rax
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; CHECK-NEXT: retq
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%ld1 = load volatile i8, i8* %p
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%arrayidx1 = getelementptr inbounds i8, i8* %p, i64 1
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@ -80,14 +75,13 @@ define i64 @sext_scalar(i8* %p, i1 zeroext %c) {
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define <2 x i64> @zext_vector_i1(<2 x i32>* %p, i1 zeroext %c) {
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; CHECK-LABEL: zext_vector_i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
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; CHECK-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
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; CHECK-NEXT: pmovzxdq {{.*#+}} xmm1 = mem[0],zero,mem[1],zero
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; CHECK-NEXT: pmovzxdq {{.*#+}} xmm0 = mem[0],zero,mem[1],zero
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; CHECK-NEXT: testl %esi, %esi
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; CHECK-NEXT: jne .LBB4_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: movdqa %xmm1, %xmm0
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; CHECK-NEXT: .LBB4_2:
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; CHECK-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
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; CHECK-NEXT: retq
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%ld1 = load volatile <2 x i32>, <2 x i32>* %p
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%arrayidx1 = getelementptr inbounds <2 x i32>, <2 x i32>* %p, i64 1
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@ -100,12 +94,11 @@ define <2 x i64> @zext_vector_i1(<2 x i32>* %p, i1 zeroext %c) {
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define <2 x i64> @zext_vector_v2i1(<2 x i32>* %p, <2 x i1> %c) {
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; CHECK-LABEL: zext_vector_v2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; CHECK-NEXT: pslld $31, %xmm0
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; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
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; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
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; CHECK-NEXT: blendvps %xmm0, %xmm2, %xmm1
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; CHECK-NEXT: pmovzxdq {{.*#+}} xmm0 = xmm1[0],zero,xmm1[1],zero
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; CHECK-NEXT: psllq $63, %xmm0
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; CHECK-NEXT: pmovzxdq {{.*#+}} xmm1 = mem[0],zero,mem[1],zero
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; CHECK-NEXT: pmovzxdq {{.*#+}} xmm2 = mem[0],zero,mem[1],zero
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; CHECK-NEXT: blendvpd %xmm0, %xmm2, %xmm1
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; CHECK-NEXT: movapd %xmm1, %xmm0
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; CHECK-NEXT: retq
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%ld1 = load volatile <2 x i32>, <2 x i32>* %p
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%arrayidx1 = getelementptr inbounds <2 x i32>, <2 x i32>* %p, i64 1
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@ -119,14 +112,13 @@ define <2 x i64> @zext_vector_v2i1(<2 x i32>* %p, <2 x i1> %c) {
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define <2 x i64> @sext_vector_i1(<2 x i32>* %p, i1 zeroext %c) {
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; CHECK-LABEL: sext_vector_i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movq {{.*#+}} xmm1 = mem[0],zero
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; CHECK-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
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; CHECK-NEXT: pmovsxdq (%rdi), %xmm1
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; CHECK-NEXT: pmovsxdq 8(%rdi), %xmm0
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; CHECK-NEXT: testl %esi, %esi
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; CHECK-NEXT: jne .LBB6_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: movdqa %xmm1, %xmm0
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; CHECK-NEXT: .LBB6_2:
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; CHECK-NEXT: pmovsxdq %xmm0, %xmm0
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; CHECK-NEXT: retq
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%ld1 = load volatile <2 x i32>, <2 x i32>* %p
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%arrayidx1 = getelementptr inbounds <2 x i32>, <2 x i32>* %p, i64 1
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@ -139,12 +131,11 @@ define <2 x i64> @sext_vector_i1(<2 x i32>* %p, i1 zeroext %c) {
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define <2 x i64> @sext_vector_v2i1(<2 x i32>* %p, <2 x i1> %c) {
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; CHECK-LABEL: sext_vector_v2i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
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; CHECK-NEXT: pslld $31, %xmm0
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; CHECK-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
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; CHECK-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
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; CHECK-NEXT: blendvps %xmm0, %xmm2, %xmm1
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; CHECK-NEXT: pmovsxdq %xmm1, %xmm0
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; CHECK-NEXT: psllq $63, %xmm0
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; CHECK-NEXT: pmovsxdq (%rdi), %xmm1
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; CHECK-NEXT: pmovsxdq 8(%rdi), %xmm2
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; CHECK-NEXT: blendvpd %xmm0, %xmm2, %xmm1
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; CHECK-NEXT: movapd %xmm1, %xmm0
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; CHECK-NEXT: retq
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%ld1 = load volatile <2 x i32>, <2 x i32>* %p
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%arrayidx1 = getelementptr inbounds <2 x i32>, <2 x i32>* %p, i64 1
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