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AMDGPU/GlobalISel: Allow scalar s1 and/or/xor 

If a 1-bit value is in a 32-bit VGPR, the scalar opcodes set SCC to
whether the result is 0. If the inputs are SCC, these can be copied to
a 32-bit SGPR to produce an SCC result.

llvm-svn: 366125
This commit is contained in:
Matt Arsenault 2019-07-15 20:20:18 +00:00
parent dfcd4384cb
commit 66ee934440
6 changed files with 1964 additions and 168 deletions
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97
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
View File

@ -108,14 +108,22 @@ AMDGPURegisterBankInfo::AMDGPURegisterBankInfo(const TargetRegisterInfo &TRI)
unsigned AMDGPURegisterBankInfo::copyCost(const RegisterBank &Dst,
const RegisterBank &Src,
unsigned Size) const {
// TODO: Should there be a UniformVGPRRegBank which can use readfirstlane?
if (Dst.getID() == AMDGPU::SGPRRegBankID &&
Src.getID() == AMDGPU::VGPRRegBankID) {
return std::numeric_limits<unsigned>::max();
}
// SGPRRegBank with size 1 is actually vcc or another 64-bit sgpr written by
// the valu.
if (Size == 1 && Dst.getID() == AMDGPU::SCCRegBankID &&
// Bool values are tricky, because the meaning is based on context. The SCC
// and VCC banks are for the natural scalar and vector conditions produced by
// a compare.
//
// Legalization doesn't know about the necessary context, so an s1 use may
// have been a truncate from an arbitrary value, in which case a copy (lowered
// as a compare with 0) needs to be inserted.
if (Size == 1 &&
(Dst.getID() == AMDGPU::SCCRegBankID ||
Dst.getID() == AMDGPU::SGPRRegBankID) &&
(Src.getID() == AMDGPU::SGPRRegBankID ||
Src.getID() == AMDGPU::VGPRRegBankID ||
Src.getID() == AMDGPU::VCCRegBankID))
@ -333,6 +341,35 @@ AMDGPURegisterBankInfo::getInstrAlternativeMappings(
case TargetOpcode::G_OR:
case TargetOpcode::G_XOR: {
unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
if (Size == 1) {
// s_{and|or|xor}_b32 set scc when the result of the 32-bit op is not 0.
const InstructionMapping &SCCMapping = getInstructionMapping(
1, 1, getOperandsMapping(
{AMDGPU::getValueMapping(AMDGPU::SCCRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
3); // Num Operands
AltMappings.push_back(&SCCMapping);
const InstructionMapping &SGPRMapping = getInstructionMapping(
1, 1, getOperandsMapping(
{AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::SGPRRegBankID, Size)}),
3); // Num Operands
AltMappings.push_back(&SGPRMapping);
const InstructionMapping &VCCMapping0 = getInstructionMapping(
2, 10, getOperandsMapping(
{AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, Size),
AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, Size)}),
3); // Num Operands
AltMappings.push_back(&VCCMapping0);
return AltMappings;
}
if (Size != 64)
break;
@ -360,7 +397,7 @@ AMDGPURegisterBankInfo::getInstrAlternativeMappings(
3); // Num Operands
AltMappings.push_back(&SVMapping);
// SGPR in LHS is slightly preferrable, so make it VS more expnesive than
// SGPR in LHS is slightly preferrable, so make it VS more expensive than
// SV.
const InstructionMapping &VSMapping = getInstructionMapping(
3, 4, getOperandsMapping(
@ -1551,8 +1588,56 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
case AMDGPU::G_XOR: {
unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
if (Size == 1) {
OpdsMapping[0] = OpdsMapping[1] =
OpdsMapping[2] = AMDGPU::getValueMapping(AMDGPU::VCCRegBankID, Size);
const RegisterBank *DstBank
= getRegBank(MI.getOperand(0).getReg(), MRI, *TRI);
unsigned TargetBankID = -1;
unsigned BankLHS = -1;
unsigned BankRHS = -1;
if (DstBank) {
TargetBankID = DstBank->getID();
if (DstBank == &AMDGPU::VCCRegBank) {
TargetBankID = AMDGPU::VCCRegBankID;
BankLHS = AMDGPU::VCCRegBankID;
BankRHS = AMDGPU::VCCRegBankID;
} else if (DstBank == &AMDGPU::SCCRegBank) {
TargetBankID = AMDGPU::SCCRegBankID;
BankLHS = AMDGPU::SGPRRegBankID;
BankRHS = AMDGPU::SGPRRegBankID;
} else {
BankLHS = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI,
AMDGPU::SGPRRegBankID);
BankRHS = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI,
AMDGPU::SGPRRegBankID);
}
} else {
BankLHS = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI,
AMDGPU::VCCRegBankID);
BankRHS = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI,
AMDGPU::VCCRegBankID);
// Both inputs should be true booleans to produce a boolean result.
if (BankLHS == AMDGPU::VGPRRegBankID || BankRHS == AMDGPU::VGPRRegBankID) {
TargetBankID = AMDGPU::VGPRRegBankID;
} else if (BankLHS == AMDGPU::VCCRegBankID || BankRHS == AMDGPU::VCCRegBankID) {
TargetBankID = AMDGPU::VCCRegBankID;
BankLHS = AMDGPU::VCCRegBankID;
BankRHS = AMDGPU::VCCRegBankID;
} else if (BankLHS == AMDGPU::SGPRRegBankID && BankRHS == AMDGPU::SGPRRegBankID) {
TargetBankID = AMDGPU::SGPRRegBankID;
} else if (BankLHS == AMDGPU::SCCRegBankID || BankRHS == AMDGPU::SCCRegBankID) {
// The operation must be done on a 32-bit register, but it will set
// scc. The result type could interchangably be SCC or SGPR, since
// both values will be produced.
TargetBankID = AMDGPU::SCCRegBankID;
BankLHS = AMDGPU::SGPRRegBankID;
BankRHS = AMDGPU::SGPRRegBankID;
}
}
OpdsMapping[0] = AMDGPU::getValueMapping(TargetBankID, Size);
OpdsMapping[1] = AMDGPU::getValueMapping(BankLHS, Size);
OpdsMapping[2] = AMDGPU::getValueMapping(BankRHS, Size);
break;
}

527
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir Normal file
View File

@ -0,0 +1,527 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck -check-prefix=FAST %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck -check-prefix=GREEDY %s
---
name: and_s1_sgpr_sgpr
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; FAST-LABEL: name: and_s1_sgpr_sgpr
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; FAST: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
; GREEDY-LABEL: name: and_s1_sgpr_sgpr
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; GREEDY: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s1) = G_TRUNC %0
%3:_(s1) = G_TRUNC %1
%4:_(s1) = G_AND %2, %3
...
---
name: and_s1_scc_scc
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; FAST-LABEL: name: and_s1_scc_scc
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; FAST: [[ICMP1:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; FAST: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
; FAST: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
; FAST: [[AND:%[0-9]+]]:scc(s1) = G_AND [[COPY2]], [[COPY3]]
; GREEDY-LABEL: name: and_s1_scc_scc
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; GREEDY: [[ICMP1:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
; GREEDY: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
; GREEDY: [[AND:%[0-9]+]]:scc(s1) = G_AND [[COPY2]], [[COPY3]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = G_CONSTANT i32 0
%3:_(s1) = G_ICMP intpred(eq), %0, %2
%4:_(s1) = G_ICMP intpred(eq), %1, %2
%5:_(s1) = G_AND %3, %4
...
---
name: and_s1_vgpr_vgpr
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; FAST-LABEL: name: and_s1_vgpr_vgpr
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
; FAST: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)
; FAST: [[AND:%[0-9]+]]:vgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
; GREEDY-LABEL: name: and_s1_vgpr_vgpr
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
; GREEDY: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)
; GREEDY: [[AND:%[0-9]+]]:vgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s1) = G_TRUNC %0
%3:_(s1) = G_TRUNC %1
%4:_(s1) = G_AND %2, %3
...
---
name: and_s1_vcc_vcc
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; FAST-LABEL: name: and_s1_vcc_vcc
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; FAST: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; FAST: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
; GREEDY-LABEL: name: and_s1_vcc_vcc
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; GREEDY: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; GREEDY: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_CONSTANT i32 0
%3:_(s1) = G_ICMP intpred(eq), %0, %2
%4:_(s1) = G_ICMP intpred(eq), %1, %2
%5:_(s1) = G_AND %3, %4
...
---
name: and_s1_sgpr_vgpr
legalized: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
; FAST-LABEL: name: and_s1_sgpr_vgpr
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; FAST: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)
; FAST: [[AND:%[0-9]+]]:vgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
; GREEDY-LABEL: name: and_s1_sgpr_vgpr
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; GREEDY: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)
; GREEDY: [[AND:%[0-9]+]]:vgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0
%2:_(s1) = G_TRUNC %0
%3:_(s1) = G_TRUNC %1
%4:_(s1) = G_AND %2, %3
...
---
name: and_s1_vgpr_sgpr
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr0
; FAST-LABEL: name: and_s1_vgpr_sgpr
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; FAST: [[AND:%[0-9]+]]:vgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
; GREEDY-LABEL: name: and_s1_vgpr_sgpr
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; GREEDY: [[AND:%[0-9]+]]:vgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0
%2:_(s1) = G_TRUNC %0
%3:_(s1) = G_TRUNC %1
%4:_(s1) = G_AND %2, %3
...
# FIXME: Should just change the result bank of the scc compare.
---
name: and_s1_scc_vcc
legalized: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
; FAST-LABEL: name: and_s1_scc_vcc
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; FAST: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; FAST: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
; FAST: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[ICMP1]]
; GREEDY-LABEL: name: and_s1_scc_vcc
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; GREEDY: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; GREEDY: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
; GREEDY: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[ICMP1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0
%2:_(s32) = G_CONSTANT i32 0
%3:_(s1) = G_ICMP intpred(eq), %0, %2
%4:_(s1) = G_ICMP intpred(eq), %1, %2
%5:_(s1) = G_AND %3, %4
...
---
name: and_s1_vcc_scc
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; FAST-LABEL: name: and_s1_vcc_scc
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; FAST: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; FAST: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; FAST: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
; GREEDY-LABEL: name: and_s1_vcc_scc
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]
; GREEDY: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY1]](s32), [[C]]
; GREEDY: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_CONSTANT i32 0
%3:_(s1) = G_ICMP intpred(eq), %0, %2
%4:_(s1) = G_ICMP intpred(eq), %1, %2
%5:_(s1) = G_AND %3, %4
...
# Test with a known result bank
---
name: and_s1_vcc_sgpr_sgpr
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; FAST-LABEL: name: and_s1_vcc_sgpr_sgpr
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; FAST: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
; FAST: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[COPY3]]
; GREEDY-LABEL: name: and_s1_vcc_sgpr_sgpr
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; GREEDY: [[AND:%[0-9]+]]:scc(s1) = G_AND [[TRUNC]], [[TRUNC1]]
; GREEDY: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[AND]](s1)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s1) = G_TRUNC %0
%3:_(s1) = G_TRUNC %1
%4:vcc(s1) = G_AND %2, %3
...
---
name: and_s1_vcc_vgpr_vgpr
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; FAST-LABEL: name: and_s1_vcc_vgpr_vgpr
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
; FAST: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)
; FAST: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
; FAST: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[COPY3]]
; GREEDY-LABEL: name: and_s1_vcc_vgpr_vgpr
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
; GREEDY: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)
; GREEDY: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
; GREEDY: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[COPY3]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s1) = G_TRUNC %0
%3:_(s1) = G_TRUNC %1
%4:vcc(s1) = G_AND %2, %3
...
---
name: and_s1_vcc_vgpr_sgpr
legalized: true
body: |
bb.0:
liveins: $vgpr0, $sgpr0
; FAST-LABEL: name: and_s1_vcc_vgpr_sgpr
; FAST: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; FAST: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
; FAST: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[COPY3]]
; GREEDY-LABEL: name: and_s1_vcc_vgpr_sgpr
; GREEDY: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; GREEDY: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
; GREEDY: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[COPY3]]
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $sgpr0
%2:_(s1) = G_TRUNC %0
%3:_(s1) = G_TRUNC %1
%4:vcc(s1) = G_AND %2, %3
...
---
name: and_s1_vcc_sgpr_vgpr
legalized: true
body: |
bb.0:
liveins: $vgpr0, $sgpr0
; FAST-LABEL: name: and_s1_vcc_sgpr_vgpr
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; FAST: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)
; FAST: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; FAST: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
; FAST: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[COPY3]]
; GREEDY-LABEL: name: and_s1_vcc_sgpr_vgpr
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; GREEDY: [[TRUNC1:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY1]](s32)
; GREEDY: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; GREEDY: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
; GREEDY: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[COPY3]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0
%2:_(s1) = G_TRUNC %0
%3:_(s1) = G_TRUNC %1
%4:vcc(s1) = G_AND %2, %3
...
---
name: and_s1_vgpr_sgpr_sgpr
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; FAST-LABEL: name: and_s1_vgpr_sgpr_sgpr
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; FAST: [[AND:%[0-9]+]]:vgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
; GREEDY-LABEL: name: and_s1_vgpr_sgpr_sgpr
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; GREEDY: [[AND:%[0-9]+]]:vgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s1) = G_TRUNC %0
%3:_(s1) = G_TRUNC %1
%4:vgpr(s1) = G_AND %2, %3
...
---
name: and_s1_sgpr_sgpr_sgpr
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; FAST-LABEL: name: and_s1_sgpr_sgpr_sgpr
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; FAST: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
; GREEDY-LABEL: name: and_s1_sgpr_sgpr_sgpr
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; GREEDY: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[TRUNC]], [[TRUNC1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s1) = G_TRUNC %0
%3:_(s1) = G_TRUNC %1
%4:sgpr(s1) = G_AND %2, %3
...
---
name: and_s1_scc_sgpr_sgpr
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; FAST-LABEL: name: and_s1_scc_sgpr_sgpr
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; FAST: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; FAST: [[AND:%[0-9]+]]:scc(s1) = G_AND [[TRUNC]], [[TRUNC1]]
; GREEDY-LABEL: name: and_s1_scc_sgpr_sgpr
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; GREEDY: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; GREEDY: [[AND:%[0-9]+]]:scc(s1) = G_AND [[TRUNC]], [[TRUNC1]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s1) = G_TRUNC %0
%3:_(s1) = G_TRUNC %1
%4:scc(s1) = G_AND %2, %3
...
---
name: and_s1_scc_scc_scc
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; FAST-LABEL: name: and_s1_scc_scc_scc
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
; FAST: [[ICMP1:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
; FAST: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
; FAST: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
; FAST: [[AND:%[0-9]+]]:scc(s1) = G_AND [[COPY2]], [[COPY3]]
; GREEDY-LABEL: name: and_s1_scc_scc_scc
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
; GREEDY: [[ICMP1:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
; GREEDY: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
; GREEDY: [[AND:%[0-9]+]]:scc(s1) = G_AND [[COPY2]], [[COPY3]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = G_CONSTANT i32 0
%3:_(s1) = G_ICMP intpred(ne), %0, %2
%4:_(s1) = G_ICMP intpred(ne), %1, %2
%5:scc(s1) = G_AND %3, %4
...
---
name: and_s1_scc_sgpr_scc
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; FAST-LABEL: name: and_s1_scc_sgpr_scc
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
; FAST: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
; FAST: [[AND:%[0-9]+]]:scc(s1) = G_AND [[TRUNC]], [[COPY2]]
; GREEDY-LABEL: name: and_s1_scc_sgpr_scc
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
; GREEDY: [[AND:%[0-9]+]]:scc(s1) = G_AND [[TRUNC]], [[COPY2]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = G_CONSTANT i32 0
%3:_(s1) = G_TRUNC %0
%4:_(s1) = G_ICMP intpred(ne), %1, %2
%5:scc(s1) = G_AND %3, %4
...
---
name: and_s1_scc_scc_sgpr
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; FAST-LABEL: name: and_s1_scc_scc_sgpr
; FAST: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; FAST: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; FAST: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; FAST: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
; FAST: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; FAST: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
; FAST: [[AND:%[0-9]+]]:scc(s1) = G_AND [[COPY2]], [[TRUNC]]
; GREEDY-LABEL: name: and_s1_scc_scc_sgpr
; GREEDY: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GREEDY: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; GREEDY: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; GREEDY: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
; GREEDY: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; GREEDY: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
; GREEDY: [[AND:%[0-9]+]]:scc(s1) = G_AND [[COPY2]], [[TRUNC]]
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = G_CONSTANT i32 0
%3:_(s1) = G_ICMP intpred(ne), %0, %2
%4:_(s1) = G_TRUNC %1
%5:scc(s1) = G_AND %3, %4
...

145
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
View File

@ -67,150 +67,6 @@ body: |
%2:_(s32) = G_AND %0, %1
...
---
name: and_i1_scc_scc
legalized: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: and_i1_scc_scc
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
; CHECK: [[ICMP1:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[ICMP1]](s1)
; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[COPY3]]
; CHECK: S_NOP 0, implicit [[AND]](s1)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s32) = G_CONSTANT i32 0
%4:_(s1) = G_ICMP intpred(ne), %0, %2
%5:_(s1) = G_ICMP intpred(ne), %1, %2
%6:_(s1) = G_AND %4, %5
S_NOP 0, implicit %6
...
---
name: and_i1_vcc_vcc
legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; CHECK-LABEL: name: and_i1_vcc_vcc
; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]
; CHECK: S_NOP 0, implicit [[AND]](s1)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:_(s32) = G_CONSTANT i32 0
%4:_(s1) = G_ICMP intpred(ne), %0, %2
%5:_(s1) = G_ICMP intpred(ne), %1, %2
%6:_(s1) = G_AND %4, %5
S_NOP 0, implicit %6
...
---
name: and_i1_scc_vcc
legalized: true
body: |
bb.0:
liveins: $sgpr0, $vgpr0
; CHECK-LABEL: name: and_i1_scc_vcc
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
; CHECK: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[ICMP1]]
; CHECK: S_NOP 0, implicit [[AND]](s1)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0
%2:_(s32) = G_CONSTANT i32 0
%4:_(s1) = G_ICMP intpred(ne), %0, %2
%5:_(s1) = G_ICMP intpred(ne), %1, %2
%6:_(s1) = G_AND %4, %5
S_NOP 0, implicit %6
...
---
name: and_i1_sgpr_trunc_sgpr_trunc
legalized: true
body: |
bb.0.entry:
liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: and_i1_sgpr_trunc_sgpr_trunc
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[COPY3]]
; CHECK: S_NOP 0, implicit [[AND]](s1)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s1) = G_TRUNC %0
%3:_(s1) = G_TRUNC %1
%4:_(s1) = G_AND %2, %3
S_NOP 0, implicit %4
...
---
name: and_i1_trunc_scc
legalized: true
body: |
bb.0.entry:
liveins: $sgpr0, $sgpr1
; CHECK-LABEL: name: and_i1_trunc_scc
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[COPY3]]
; CHECK: S_NOP 0, implicit [[AND]](s1)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
%2:_(s1) = G_TRUNC %0
%3:_(s1) = G_ICMP intpred(ne), %0, %1
%4:_(s1) = G_AND %2, %3
S_NOP 0, implicit %4
...
---
name: and_i1_s_trunc_vcc
legalized: true
body: |
bb.0.entry:
liveins: $sgpr0, $vgpr0
; CHECK-LABEL: name: and_i1_s_trunc_vcc
; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; CHECK: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; CHECK: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[COPY2]], [[ICMP]]
; CHECK: S_NOP 0, implicit [[AND]](s1)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $vgpr0
%2:_(s1) = G_TRUNC %0
%3:_(s1) = G_ICMP intpred(ne), %0, %1
%4:_(s1) = G_AND %2, %3
S_NOP 0, implicit %4
...
---
name: and_s64_ss
legalized: true
@ -737,3 +593,4 @@ body: |
%1:_(<2 x s16>) = COPY $vgpr1
%2:_(<2 x s16>) = G_AND %0, %1
...

15
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
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@ -80,9 +80,9 @@ body: |
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
; CHECK: [[ICMP1:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[ICMP1]](s1)
; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[COPY2]], [[COPY3]]
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
; CHECK: [[OR:%[0-9]+]]:scc(s1) = G_OR [[COPY2]], [[COPY3]]
; CHECK: S_NOP 0, implicit [[OR]](s1)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
@ -153,9 +153,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[COPY2]], [[COPY3]]
; CHECK: [[OR:%[0-9]+]]:sgpr(s1) = G_OR [[TRUNC]], [[TRUNC1]]
; CHECK: S_NOP 0, implicit [[OR]](s1)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
@ -177,9 +175,8 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
; CHECK: [[OR:%[0-9]+]]:vcc(s1) = G_OR [[COPY2]], [[COPY3]]
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
; CHECK: [[OR:%[0-9]+]]:scc(s1) = G_OR [[TRUNC]], [[COPY2]]
; CHECK: S_NOP 0, implicit [[OR]](s1)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1

1333
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir Normal file
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15
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
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@ -80,9 +80,9 @@ body: |
; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[C]]
; CHECK: [[ICMP1:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY1]](s32), [[C]]
; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[ICMP1]](s1)
; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[COPY2]], [[COPY3]]
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
; CHECK: [[COPY3:%[0-9]+]]:sgpr(s1) = COPY [[ICMP1]](s1)
; CHECK: [[XOR:%[0-9]+]]:scc(s1) = G_XOR [[COPY2]], [[COPY3]]
; CHECK: S_NOP 0, implicit [[XOR]](s1)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
@ -153,9 +153,7 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY1]](s32)
; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[TRUNC1]](s1)
; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[COPY2]], [[COPY3]]
; CHECK: [[XOR:%[0-9]+]]:sgpr(s1) = G_XOR [[TRUNC]], [[TRUNC1]]
; CHECK: S_NOP 0, implicit [[XOR]](s1)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1
@ -177,9 +175,8 @@ body: |
; CHECK: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
; CHECK: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
; CHECK: [[ICMP:%[0-9]+]]:scc(s1) = G_ICMP intpred(ne), [[COPY]](s32), [[COPY1]]
; CHECK: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; CHECK: [[COPY3:%[0-9]+]]:vcc(s1) = COPY [[ICMP]](s1)
; CHECK: [[XOR:%[0-9]+]]:vcc(s1) = G_XOR [[COPY2]], [[COPY3]]
; CHECK: [[COPY2:%[0-9]+]]:sgpr(s1) = COPY [[ICMP]](s1)
; CHECK: [[XOR:%[0-9]+]]:scc(s1) = G_XOR [[TRUNC]], [[COPY2]]
; CHECK: S_NOP 0, implicit [[XOR]](s1)
%0:_(s32) = COPY $sgpr0
%1:_(s32) = COPY $sgpr1