forked from OSchip/llvm-project
[RISCV][Clang] Add some RVV Integer intrinsic functions.
1. Rename RVVBinBuiltin to RVVOutputOp1Builtin because it is not related to the number of operand. 2. Add RVV Integer instuctions which use RVVOutputOp1Builtin. Reviewed By: craig.topper Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Differential Revision: https://reviews.llvm.org/D99524
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@ -200,24 +200,58 @@ class RVVBuiltin<string suffix, string prototype, string type_range,
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// Basic classes with automatic codegen.
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//===----------------------------------------------------------------------===//
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class RVVBinBuiltin<string suffix, string prototype, string type_range>
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: RVVBuiltin<suffix, prototype, type_range> {
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let IntrinsicTypes = [-1, 1];
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}
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multiclass RVVBinBuiltinSet<string intrinsic_name, string type_range,
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list<list<string>> suffixes_prototypes> {
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let IRName = intrinsic_name, IRNameMask = intrinsic_name # "_mask" in {
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multiclass RVVBuiltinSet<string intrinsic_name, string type_range,
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list<list<string>> suffixes_prototypes,
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list<int> intrinsic_types> {
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let IRName = intrinsic_name, IRNameMask = intrinsic_name # "_mask",
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IntrinsicTypes = intrinsic_types in {
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foreach s_p = suffixes_prototypes in {
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let Name = NAME # "_" # s_p[0] in {
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defvar suffix = s_p[1];
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defvar prototype = s_p[2];
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def : RVVBinBuiltin<suffix, prototype, type_range>;
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def : RVVBuiltin<suffix, prototype, type_range>;
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}
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}
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}
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}
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// IntrinsicTypes is output, op1 [-1, 1]
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multiclass RVVOutOp1BuiltinSet<string intrinsic_name, string type_range,
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list<list<string>> suffixes_prototypes> {
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defm "" : RVVBuiltinSet<intrinsic_name, type_range, suffixes_prototypes, [-1, 1]>;
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}
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multiclass RVVSignedBinBuiltinSet {
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defm "" : RVVOutOp1BuiltinSet<NAME, "csil",
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[["vv", "v", "vvv"],
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["vx", "v", "vve"]]>;
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}
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multiclass RVVUnsignedBinBuiltinSet {
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defm "" : RVVOutOp1BuiltinSet<NAME, "csil",
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[["vv", "Uv", "UvUvUv"],
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["vx", "Uv", "UvUvUe"]]>;
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}
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multiclass RVVIntBinBuiltinSet {
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defm "" : RVVSignedBinBuiltinSet;
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defm "" : RVVUnsignedBinBuiltinSet;
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}
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multiclass RVVIntTerBuiltinSet {
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defm "" : RVVOutOp1BuiltinSet<NAME, "csil",
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[["vv", "v", "vvvv"],
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["vx", "v", "vvev"],
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["vv", "Uv", "UvUvUvUv"],
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["vx", "Uv", "UvUvUeUv"]]>;
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}
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multiclass RVVFloatingBinBuiltinSet {
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defm "" : RVVOutOp1BuiltinSet<NAME, "fd",
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[["vv", "v", "vvv"],
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["vf", "v", "vve"]]>;
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}
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defvar TypeList = ["c","s","i","l","f","d"];
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defvar EEWList = [["8", "(Log2EEW:3)"],
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["16", "(Log2EEW:4)"],
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@ -387,14 +421,85 @@ defm : RVVIndexedLoad<"vloxei">;
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// 12. Vector Integer Arithmetic Instructions
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// 12.1. Vector Single-Width Integer Add and Subtract
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defm vadd : RVVBinBuiltinSet<"vadd", "csil",
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[["vv", "v", "vvv"],
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["vx", "v", "vve"],
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["vv", "Uv", "UvUvUv"],
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["vx", "Uv", "UvUvUe"]]>;
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defm vadd : RVVIntBinBuiltinSet;
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defm vsub : RVVIntBinBuiltinSet;
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defm vrsub : RVVOutOp1BuiltinSet<"vrsub", "csil",
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[["vx", "v", "vve"],
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["vx", "Uv", "UvUvUe"]]>;
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// 12.2. Vector Widening Integer Add/Subtract
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// TODO
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// 12.3. Vector Integer Extension
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// TODO
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// 12.4. Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
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// TODO
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// 12.5. Vector Bitwise Logical Instructions
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defm vand : RVVIntBinBuiltinSet;
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defm vxor : RVVIntBinBuiltinSet;
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defm vor : RVVIntBinBuiltinSet;
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// 12.6. Vector Single-Width Bit Shift Instructions
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defm vsll : RVVOutOp1BuiltinSet<"vsll", "csil",
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[["vv", "v", "vvUv"],
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["vx", "v", "vvz"],
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["vv", "Uv", "UvUvUv"],
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["vx", "Uv", "UvUvz"]]>;
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defm vsrl : RVVOutOp1BuiltinSet<"vsrl", "csil",
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[["vv", "Uv", "UvUvUv"],
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["vx", "Uv", "UvUvz"]]>;
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defm vsra : RVVOutOp1BuiltinSet<"vsra", "csil",
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[["vv", "v", "vvUv"],
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["vx", "v", "vvz"]]>;
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// 12.7. Vector Narrowing Integer Right Shift Instructions
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// TODO
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// 12.8. Vector Integer Comparison Instructions
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// TODO
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// 12.9. Vector Integer Min/Max Instructions
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defm vminu : RVVUnsignedBinBuiltinSet;
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defm vmin : RVVSignedBinBuiltinSet;
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defm vmaxu : RVVUnsignedBinBuiltinSet;
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defm vmax : RVVSignedBinBuiltinSet;
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// 12.10. Vector Single-Width Integer Multiply Instructions
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defm vmul : RVVIntBinBuiltinSet;
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defm vmulh : RVVSignedBinBuiltinSet;
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defm vmulhu : RVVUnsignedBinBuiltinSet;
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defm vmulhsu : RVVOutOp1BuiltinSet<"vmulhsu", "csil",
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[["vv", "v", "vvUv"],
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["vx", "v", "vvUe"]]>;
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// 12.11. Vector Integer Divide Instructions
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defm vdivu : RVVUnsignedBinBuiltinSet;
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defm vdiv : RVVSignedBinBuiltinSet;
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defm vremu : RVVUnsignedBinBuiltinSet;
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defm vrem : RVVSignedBinBuiltinSet;
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// 12.12. Vector Widening Integer Multiply Instructions
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// TODO
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// 12.13. Vector Single-Width Integer Multiply-Add Instructions
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let HasMaskedOffOperand = false in {
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defm vmacc : RVVIntTerBuiltinSet;
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defm vnmsac : RVVIntTerBuiltinSet;
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defm vmadd : RVVIntTerBuiltinSet;
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defm vnmsub : RVVIntTerBuiltinSet;
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}
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// 12.14. Vector Widening Integer Multiply-Add Instructions
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// TODO
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// 12.15. Vector Integer Merge Instructions
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// TODO
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// 12.16. Vector Integer Move Instructions
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// TODO
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// 14. Vector Floating-Point Instructions
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// 14.2. Vector Single-Width Floating-Point Add/Subtract Instructions
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defm vfadd : RVVBinBuiltinSet<"vfadd", "fd",
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[["vv", "v", "vvv"],
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["vf", "v", "vve"]]>;
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defm vfadd : RVVFloatingBinBuiltinSet;
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