diff --git a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp index 768d54fc9c24..ddd28d095e51 100644 --- a/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp @@ -72,7 +72,7 @@ void Mips16DAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) { MachineRegisterInfo &RegInfo = MF.getRegInfo(); const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); DebugLoc DL; - Register V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(); + Register V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(MF); const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass; V0 = RegInfo.createVirtualRegister(RC); diff --git a/llvm/lib/Target/Mips/Mips16ISelLowering.cpp b/llvm/lib/Target/Mips/Mips16ISelLowering.cpp index 5425df77d9b8..a3b86bdc2ca0 100644 --- a/llvm/lib/Target/Mips/Mips16ISelLowering.cpp +++ b/llvm/lib/Target/Mips/Mips16ISelLowering.cpp @@ -492,7 +492,7 @@ getOpndList(SmallVectorImpl &Ops, ExternalSymbolSDNode *S = cast(JumpTarget); JumpTarget = getAddrGlobal(S, CLI.DL, JumpTarget.getValueType(), DAG, MipsII::MO_GOT, Chain, - FuncInfo->callPtrInfo(S->getSymbol())); + FuncInfo->callPtrInfo(MF, S->getSymbol())); } else RegsToPass.push_front(std::make_pair((unsigned)Mips::T9, Callee)); } diff --git a/llvm/lib/Target/Mips/MipsCallLowering.cpp b/llvm/lib/Target/Mips/MipsCallLowering.cpp index d7f02683abf2..cffd99affac1 100644 --- a/llvm/lib/Target/Mips/MipsCallLowering.cpp +++ b/llvm/lib/Target/Mips/MipsCallLowering.cpp @@ -593,7 +593,7 @@ bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder, if (IsCalleeGlobalPIC) { MIRBuilder.buildCopy( Register(Mips::GP), - MF.getInfo()->getGlobalBaseRegForGlobalISel()); + MF.getInfo()->getGlobalBaseRegForGlobalISel(MF)); MIB.addDef(Mips::GP, RegState::Implicit); } MIRBuilder.insertInstr(MIB); diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp index 1b6a75e7c383..8a847eaf6618 100644 --- a/llvm/lib/Target/Mips/MipsFastISel.cpp +++ b/llvm/lib/Target/Mips/MipsFastISel.cpp @@ -420,7 +420,7 @@ unsigned MipsFastISel::materializeGV(const GlobalValue *GV, MVT VT) { if (IsThreadLocal) return 0; emitInst(Mips::LW, DestReg) - .addReg(MFI->getGlobalBaseReg()) + .addReg(MFI->getGlobalBaseReg(*MF)) .addGlobalAddress(GV, 0, MipsII::MO_GOT); if ((GV->hasInternalLinkage() || (GV->hasLocalLinkage() && !isa(GV)))) { @@ -437,7 +437,7 @@ unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) { const TargetRegisterClass *RC = &Mips::GPR32RegClass; unsigned DestReg = createResultReg(RC); emitInst(Mips::LW, DestReg) - .addReg(MFI->getGlobalBaseReg()) + .addReg(MFI->getGlobalBaseReg(*MF)) .addSym(Sym, MipsII::MO_GOT); return DestReg; } diff --git a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp index 37df04e3cbb5..d88696525e9e 100644 --- a/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -65,7 +65,7 @@ bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { /// getGlobalBaseReg - Output the instructions required to put the /// GOT address into a register. SDNode *MipsDAGToDAGISel::getGlobalBaseReg() { - Register GlobalBaseReg = MF->getInfo()->getGlobalBaseReg(); + Register GlobalBaseReg = MF->getInfo()->getGlobalBaseReg(*MF); return CurDAG->getRegister(GlobalBaseReg, getTargetLowering()->getPointerTy( CurDAG->getDataLayout())) .getNode(); diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index 419e31acee32..2da35020006e 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -142,8 +142,9 @@ unsigned MipsTargetLowering::getVectorTypeBreakdownForCallingConv( } SDValue MipsTargetLowering::getGlobalReg(SelectionDAG &DAG, EVT Ty) const { - MipsFunctionInfo *FI = DAG.getMachineFunction().getInfo(); - return DAG.getRegister(FI->getGlobalBaseReg(), Ty); + MachineFunction &MF = DAG.getMachineFunction(); + MipsFunctionInfo *FI = MF.getInfo(); + return DAG.getRegister(FI->getGlobalBaseReg(MF), Ty); } SDValue MipsTargetLowering::getTargetNode(GlobalAddressSDNode *N, EVT Ty, @@ -3420,11 +3421,11 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, else if (Subtarget.useXGOT()) { Callee = getAddrGlobalLargeGOT(G, DL, Ty, DAG, MipsII::MO_CALL_HI16, MipsII::MO_CALL_LO16, Chain, - FuncInfo->callPtrInfo(Val)); + FuncInfo->callPtrInfo(MF, Val)); IsCallReloc = true; } else { Callee = getAddrGlobal(G, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, - FuncInfo->callPtrInfo(Val)); + FuncInfo->callPtrInfo(MF, Val)); IsCallReloc = true; } } else @@ -3442,11 +3443,11 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, else if (Subtarget.useXGOT()) { Callee = getAddrGlobalLargeGOT(S, DL, Ty, DAG, MipsII::MO_CALL_HI16, MipsII::MO_CALL_LO16, Chain, - FuncInfo->callPtrInfo(Sym)); + FuncInfo->callPtrInfo(MF, Sym)); IsCallReloc = true; } else { // PIC Callee = getAddrGlobal(S, DL, Ty, DAG, MipsII::MO_GOT_CALL, Chain, - FuncInfo->callPtrInfo(Sym)); + FuncInfo->callPtrInfo(MF, Sym)); IsCallReloc = true; } diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp index 3f63f40b9017..256fb74c1d6c 100644 --- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp +++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp @@ -404,7 +404,7 @@ bool MipsInstructionSelector::select(MachineInstr &I) { .addDef(Dest) .addUse(DestTmp) .addUse(MF.getInfo() - ->getGlobalBaseRegForGlobalISel()); + ->getGlobalBaseRegForGlobalISel(MF)); if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI)) return false; } @@ -669,7 +669,7 @@ bool MipsInstructionSelector::select(MachineInstr &I) { MachineInstr *LWGOT = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) .addDef(I.getOperand(0).getReg()) .addReg(MF.getInfo() - ->getGlobalBaseRegForGlobalISel()) + ->getGlobalBaseRegForGlobalISel(MF)) .addGlobalAddress(GVal); // Global Values that don't have local linkage are handled differently // when they are part of call sequence. MipsCallLowering::lowerCall @@ -725,7 +725,7 @@ bool MipsInstructionSelector::select(MachineInstr &I) { MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) .addDef(I.getOperand(0).getReg()) .addReg(MF.getInfo() - ->getGlobalBaseRegForGlobalISel()) + ->getGlobalBaseRegForGlobalISel(MF)) .addJumpTableIndex(I.getOperand(1).getIndex(), MipsII::MO_GOT) .addMemOperand(MF.getMachineMemOperand( MachinePointerInfo::getGOT(MF), MachineMemOperand::MOLoad, 4, diff --git a/llvm/lib/Target/Mips/MipsMachineFunction.cpp b/llvm/lib/Target/Mips/MipsMachineFunction.cpp index 7e5c37b07976..e4b00b55bb51 100644 --- a/llvm/lib/Target/Mips/MipsMachineFunction.cpp +++ b/llvm/lib/Target/Mips/MipsMachineFunction.cpp @@ -44,22 +44,22 @@ static const TargetRegisterClass &getGlobalBaseRegClass(MachineFunction &MF) { return Mips::GPR32RegClass; } -Register MipsFunctionInfo::getGlobalBaseReg() { +Register MipsFunctionInfo::getGlobalBaseReg(MachineFunction &MF) { if (!GlobalBaseReg) GlobalBaseReg = MF.getRegInfo().createVirtualRegister(&getGlobalBaseRegClass(MF)); return GlobalBaseReg; } -Register MipsFunctionInfo::getGlobalBaseRegForGlobalISel() { +Register MipsFunctionInfo::getGlobalBaseRegForGlobalISel(MachineFunction &MF) { if (!GlobalBaseReg) { - getGlobalBaseReg(); - initGlobalBaseReg(); + getGlobalBaseReg(MF); + initGlobalBaseReg(MF); } return GlobalBaseReg; } -void MipsFunctionInfo::initGlobalBaseReg() { +void MipsFunctionInfo::initGlobalBaseReg(MachineFunction &MF) { if (!GlobalBaseReg) return; @@ -146,7 +146,7 @@ void MipsFunctionInfo::initGlobalBaseReg() { .addReg(Mips::V0).addReg(Mips::T9); } -void MipsFunctionInfo::createEhDataRegsFI() { +void MipsFunctionInfo::createEhDataRegsFI(MachineFunction &MF) { const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); for (int I = 0; I < 4; ++I) { const TargetRegisterClass &RC = @@ -159,7 +159,7 @@ void MipsFunctionInfo::createEhDataRegsFI() { } } -void MipsFunctionInfo::createISRRegFI() { +void MipsFunctionInfo::createISRRegFI(MachineFunction &MF) { // ISRs require spill slots for Status & ErrorPC Coprocessor 0 registers. // The current implementation only supports Mips32r2+ not Mips64rX. Status // is always 32 bits, ErrorPC is 32 or 64 bits dependent on architecture, @@ -180,15 +180,18 @@ bool MipsFunctionInfo::isEhDataRegFI(int FI) const { bool MipsFunctionInfo::isISRRegFI(int FI) const { return IsISR && (FI == ISRDataRegFI[0] || FI == ISRDataRegFI[1]); } -MachinePointerInfo MipsFunctionInfo::callPtrInfo(const char *ES) { +MachinePointerInfo MipsFunctionInfo::callPtrInfo(MachineFunction &MF, + const char *ES) { return MachinePointerInfo(MF.getPSVManager().getExternalSymbolCallEntry(ES)); } -MachinePointerInfo MipsFunctionInfo::callPtrInfo(const GlobalValue *GV) { +MachinePointerInfo MipsFunctionInfo::callPtrInfo(MachineFunction &MF, + const GlobalValue *GV) { return MachinePointerInfo(MF.getPSVManager().getGlobalValueCallEntry(GV)); } -int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) { +int MipsFunctionInfo::getMoveF64ViaSpillFI(MachineFunction &MF, + const TargetRegisterClass *RC) { const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); if (MoveF64ViaSpillFI == -1) { MoveF64ViaSpillFI = MF.getFrameInfo().CreateStackObject( diff --git a/llvm/lib/Target/Mips/MipsMachineFunction.h b/llvm/lib/Target/Mips/MipsMachineFunction.h index abb5dde3cf47..786d210e2aaa 100644 --- a/llvm/lib/Target/Mips/MipsMachineFunction.h +++ b/llvm/lib/Target/Mips/MipsMachineFunction.h @@ -24,7 +24,7 @@ namespace llvm { /// Mips target-specific information for each MachineFunction. class MipsFunctionInfo : public MachineFunctionInfo { public: - MipsFunctionInfo(MachineFunction &MF) : MF(MF) {} + MipsFunctionInfo(MachineFunction &MF) {} ~MipsFunctionInfo() override; @@ -32,12 +32,12 @@ public: void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } bool globalBaseRegSet() const; - Register getGlobalBaseReg(); - Register getGlobalBaseRegForGlobalISel(); + Register getGlobalBaseReg(MachineFunction &MF); + Register getGlobalBaseRegForGlobalISel(MachineFunction &MF); // Insert instructions to initialize the global base register in the // first MBB of the function. - void initGlobalBaseReg(); + void initGlobalBaseReg(MachineFunction &MF); int getVarArgsFrameIndex() const { return VarArgsFrameIndex; } void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; } @@ -53,30 +53,30 @@ public: bool callsEhReturn() const { return CallsEhReturn; } void setCallsEhReturn() { CallsEhReturn = true; } - void createEhDataRegsFI(); + void createEhDataRegsFI(MachineFunction &MF); int getEhDataRegFI(unsigned Reg) const { return EhDataRegFI[Reg]; } bool isEhDataRegFI(int FI) const; /// Create a MachinePointerInfo that has an ExternalSymbolPseudoSourceValue /// object representing a GOT entry for an external function. - MachinePointerInfo callPtrInfo(const char *ES); + MachinePointerInfo callPtrInfo(MachineFunction &MF, const char *ES); // Functions with the "interrupt" attribute require special prologues, // epilogues and additional spill slots. bool isISR() const { return IsISR; } void setISR() { IsISR = true; } - void createISRRegFI(); + void createISRRegFI(MachineFunction &MF); int getISRRegFI(Register Reg) const { return ISRDataRegFI[Reg]; } bool isISRRegFI(int FI) const; /// Create a MachinePointerInfo that has a GlobalValuePseudoSourceValue object /// representing a GOT entry for a global function. - MachinePointerInfo callPtrInfo(const GlobalValue *GV); + MachinePointerInfo callPtrInfo(MachineFunction &MF, const GlobalValue *GV); void setSaveS2() { SaveS2 = true; } bool hasSaveS2() const { return SaveS2; } - int getMoveF64ViaSpillFI(const TargetRegisterClass *RC); + int getMoveF64ViaSpillFI(MachineFunction &MF, const TargetRegisterClass *RC); std::map StubsNeeded; @@ -84,8 +84,6 @@ public: private: virtual void anchor(); - MachineFunction& MF; - /// SRetReturnReg - Some subtargets require that sret lowering includes /// returning the value of the returned struct in a register. This field /// holds the virtual register into which the sret argument is passed. diff --git a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp index f145aefc0419..35df8b28cc1e 100644 --- a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp +++ b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp @@ -320,7 +320,7 @@ bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB, // We re-use the same spill slot each time so that the stack frame doesn't // grow too much in functions with a large number of moves. - int FI = MF.getInfo()->getMoveF64ViaSpillFI(RC2); + int FI = MF.getInfo()->getMoveF64ViaSpillFI(MF, RC2); if (!Subtarget.isLittle()) std::swap(LoReg, HiReg); TII.storeRegToStack(MBB, I, LoReg, I->getOperand(1).isKill(), FI, RC, @@ -386,7 +386,7 @@ bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB, // We re-use the same spill slot each time so that the stack frame doesn't // grow too much in functions with a large number of moves. - int FI = MF.getInfo()->getMoveF64ViaSpillFI(RC); + int FI = MF.getInfo()->getMoveF64ViaSpillFI(MF, RC); TII.storeRegToStack(MBB, I, SrcReg, Op1.isKill(), FI, RC, &RegInfo, 0); TII.loadRegFromStack(MBB, I, DstReg, FI, RC2, &RegInfo, Offset); return true; @@ -878,11 +878,11 @@ void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF, // Create spill slots for eh data registers if function calls eh_return. if (MipsFI->callsEhReturn()) - MipsFI->createEhDataRegsFI(); + MipsFI->createEhDataRegsFI(MF); // Create spill slots for Coprocessor 0 registers if function is an ISR. if (MipsFI->isISR()) - MipsFI->createISRRegFI(); + MipsFI->createISRRegFI(MF); // Expand pseudo instructions which load, store or copy accumulators. // Add an emergency spill slot if a pseudo was expanded. diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index 3ddba25fcef6..7be5fc33a0af 100644 --- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -153,7 +153,7 @@ void MipsSEDAGToDAGISel::emitMCountABI(MachineInstr &MI, MachineBasicBlock &MBB, } void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) { - MF.getInfo()->initGlobalBaseReg(); + MF.getInfo()->initGlobalBaseReg(MF); MachineRegisterInfo *MRI = &MF.getRegInfo();