forked from OSchip/llvm-project
[ARM][MachineOutliner] Add LR RegSave mode.
Outline chunks of code which need to save and restore the link register when a spare register can be used to it. Differential Revision: https://reviews.llvm.org/D80127
This commit is contained in:
Yvan Roux
parent
b8ae3fdfa5
commit
669066de65
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@ -5580,11 +5580,33 @@ bool llvm::HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2,
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/// | Frame overhead in Bytes | 4 | 4 |
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/// | Stack fixup required | No | No |
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/// +-------------------------+--------+-----+
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///
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/// \p MachineOutlinerRegSave implies that the function should be called with a
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/// save and restore of LR to an available register. This allows us to avoid
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/// stack fixups. Note that this outlining variant is compatible with the
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/// NoLRSave case.
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///
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/// That is,
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///
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/// I1 Save LR OUTLINED_FUNCTION:
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/// I2 --> BL OUTLINED_FUNCTION I1
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/// I3 Restore LR I2
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/// I3
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/// BX LR
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///
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/// +-------------------------+--------+-----+
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/// | | Thumb2 | ARM |
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/// +-------------------------+--------+-----+
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/// | Call overhead in Bytes | 8 | 12 |
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/// | Frame overhead in Bytes | 2 | 4 |
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/// | Stack fixup required | No | No |
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/// +-------------------------+--------+-----+
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enum MachineOutlinerClass {
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MachineOutlinerTailCall,
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MachineOutlinerThunk,
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MachineOutlinerNoLRSave
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MachineOutlinerNoLRSave,
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MachineOutlinerRegSave
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};
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enum MachineOutlinerMBBFlags {
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@ -5600,6 +5622,8 @@ struct OutlinerCosts {
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const int FrameThunk;
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const int CallNoLRSave;
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const int FrameNoLRSave;
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const int CallRegSave;
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const int FrameRegSave;
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OutlinerCosts(const ARMSubtarget &target)
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: CallTailCall(target.isThumb() ? 4 : 4),
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@ -5607,9 +5631,33 @@ struct OutlinerCosts {
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CallThunk(target.isThumb() ? 4 : 4),
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FrameThunk(target.isThumb() ? 0 : 0),
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CallNoLRSave(target.isThumb() ? 4 : 4),
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FrameNoLRSave(target.isThumb() ? 4 : 4) {}
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FrameNoLRSave(target.isThumb() ? 4 : 4),
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CallRegSave(target.isThumb() ? 8 : 12),
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FrameRegSave(target.isThumb() ? 2 : 4) {}
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};
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unsigned
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ARMBaseInstrInfo::findRegisterToSaveLRTo(const outliner::Candidate &C) const {
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assert(C.LRUWasSet && "LRU wasn't set?");
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MachineFunction *MF = C.getMF();
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const ARMBaseRegisterInfo *ARI = static_cast<const ARMBaseRegisterInfo *>(
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MF->getSubtarget().getRegisterInfo());
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BitVector regsReserved = ARI->getReservedRegs(*MF);
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// Check if there is an available register across the sequence that we can
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// use.
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for (unsigned Reg : ARM::rGPRRegClass) {
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if (!(Reg < regsReserved.size() && regsReserved.test(Reg)) &&
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Reg != ARM::LR && // LR is not reserved, but don't use it.
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Reg != ARM::R12 && // R12 is not guaranteed to be preserved.
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C.LRU.available(Reg) && C.UsedInSequence.available(Reg))
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return Reg;
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}
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// No suitable register. Return 0.
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return 0u;
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}
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outliner::OutlinedFunction ARMBaseInstrInfo::getOutliningCandidateInfo(
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std::vector<outliner::Candidate> &RepeatedSequenceLocs) const {
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outliner::Candidate &FirstCand = RepeatedSequenceLocs[0];
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@ -5709,6 +5757,15 @@ outliner::OutlinedFunction ARMBaseInstrInfo::getOutliningCandidateInfo(
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C.setCallInfo(MachineOutlinerNoLRSave, Costs.CallNoLRSave);
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CandidatesWithoutStackFixups.push_back(C);
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}
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// Is an unused register available? If so, we won't modify the stack, so
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// we can outline with the same frame type as those that don't save LR.
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else if (findRegisterToSaveLRTo(C)) {
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FrameID = MachineOutlinerRegSave;
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NumBytesNoStackCalls += Costs.CallRegSave;
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C.setCallInfo(MachineOutlinerRegSave, Costs.CallRegSave);
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CandidatesWithoutStackFixups.push_back(C);
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}
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}
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if (!CandidatesWithoutStackFixups.empty()) {
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@ -5961,6 +6018,20 @@ MachineBasicBlock::iterator ARMBaseInstrInfo::insertOutlinedCall(
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CallMIB.add(predOps(ARMCC::AL));
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CallMIB.addGlobalAddress(M.getNamedValue(MF.getName()));
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// Can we save to a register?
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if (C.CallConstructionID == MachineOutlinerRegSave) {
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unsigned Reg = findRegisterToSaveLRTo(C);
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assert(Reg != 0 && "No callee-saved register available?");
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// Save and restore LR from that register.
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if (!MBB.isLiveIn(ARM::LR))
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MBB.addLiveIn(ARM::LR);
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copyPhysReg(MBB, It, DebugLoc(), Reg, ARM::LR, true);
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CallPt = MBB.insert(It, CallMIB);
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copyPhysReg(MBB, It, DebugLoc(), ARM::LR, Reg, true);
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It--;
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return CallPt;
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}
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// Insert the call.
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It = MBB.insert(It, CallMIB);
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return It;
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@ -373,6 +373,10 @@ public:
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const outliner::Candidate &C) const override;
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private:
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/// Returns an unused general-purpose register which can be used for
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/// constructing an outlined call if one exists. Returns 0 otherwise.
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unsigned findRegisterToSaveLRTo(const outliner::Candidate &C) const;
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unsigned getInstBundleLength(const MachineInstr &MI) const;
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int getVLDMDefCycle(const InstrItineraryData *ItinData,
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@ -0,0 +1,174 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=arm-- -run-pass=machine-outliner -verify-machineinstrs \
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# RUN: %s -o - | FileCheck %s
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--- |
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define void @outline_save_reg_arm() #0 { ret void }
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define void @outline_save_reg_thumb() #1 { ret void }
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declare void @z()
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attributes #0 = { minsize optsize }
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attributes #1 = { minsize optsize "target-features"="+armv7-a,+thumb-mode" }
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...
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---
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name: outline_save_reg_arm
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: outline_save_reg_arm
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; CHECK: bb.0:
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; CHECK: liveins: $lr
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; CHECK: $r6 = MOVr killed $lr, 14 /* CC::al */, $noreg, $noreg
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; CHECK: BL @OUTLINED_FUNCTION_1
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; CHECK: $lr = MOVr killed $r6, 14 /* CC::al */, $noreg, $noreg
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; CHECK: bb.1:
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; CHECK: liveins: $lr
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; CHECK: $r6 = MOVr killed $lr, 14 /* CC::al */, $noreg, $noreg
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; CHECK: BL @OUTLINED_FUNCTION_1
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; CHECK: $lr = MOVr killed $r6, 14 /* CC::al */, $noreg, $noreg
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; CHECK: bb.2:
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; CHECK: liveins: $lr
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; CHECK: $r0 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r1 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r2 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r3 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r4 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r5 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: bb.3:
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; CHECK: liveins: $lr, $r0, $r6, $r7, $r8, $r9, $r10, $r11
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; CHECK: $r6 = MOVr killed $lr, 14 /* CC::al */, $noreg, $noreg
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; CHECK: BL @OUTLINED_FUNCTION_1
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; CHECK: $lr = MOVr killed $r6, 14 /* CC::al */, $noreg, $noreg
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; CHECK: bb.4:
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; CHECK: liveins: $lr
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; CHECK: $r2 = MOVr $lr, 14 /* CC::al */, $noreg, $noreg
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; CHECK: BX_RET 14 /* CC::al */, $noreg
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bb.0:
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liveins: $lr
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$r0 = MOVi 1, 14, $noreg, $noreg
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$r1 = MOVi 1, 14, $noreg, $noreg
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$r2 = MOVi 1, 14, $noreg, $noreg
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$r3 = MOVi 1, 14, $noreg, $noreg
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$r4 = MOVi 1, 14, $noreg, $noreg
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$r5 = MOVi 1, 14, $noreg, $noreg
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bb.1:
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liveins: $lr
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$r0 = MOVi 1, 14, $noreg, $noreg
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$r1 = MOVi 1, 14, $noreg, $noreg
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$r2 = MOVi 1, 14, $noreg, $noreg
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$r3 = MOVi 1, 14, $noreg, $noreg
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$r4 = MOVi 1, 14, $noreg, $noreg
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$r5 = MOVi 1, 14, $noreg, $noreg
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bb.2:
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liveins: $lr
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$r0 = MOVi 1, 14, $noreg, $noreg
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$r1 = MOVi 1, 14, $noreg, $noreg
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$r2 = MOVi 1, 14, $noreg, $noreg
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$r3 = MOVi 1, 14, $noreg, $noreg
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$r4 = MOVi 1, 14, $noreg, $noreg
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$r5 = MOVi 1, 14, $noreg, $noreg
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bb.3:
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liveins: $lr, $r0, $r6, $r7, $r8, $r9, $r10, $r11
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$r0 = MOVi 1, 14, $noreg, $noreg
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$r1 = MOVi 1, 14, $noreg, $noreg
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$r2 = MOVi 1, 14, $noreg, $noreg
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$r3 = MOVi 1, 14, $noreg, $noreg
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$r4 = MOVi 1, 14, $noreg, $noreg
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$r5 = MOVi 1, 14, $noreg, $noreg
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bb.4:
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liveins: $lr
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$r2 = MOVr $lr, 14, $noreg, $noreg
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BX_RET 14, $noreg
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...
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---
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name: outline_save_reg_thumb
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: outline_save_reg_thumb
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; CHECK: bb.0:
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; CHECK: liveins: $lr
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; CHECK: $r6 = tMOVr killed $lr, 14 /* CC::al */, $noreg
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; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0
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; CHECK: $lr = tMOVr killed $r6, 14 /* CC::al */, $noreg
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; CHECK: bb.1:
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; CHECK: liveins: $lr
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; CHECK: $r6 = tMOVr killed $lr, 14 /* CC::al */, $noreg
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; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0
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; CHECK: $lr = tMOVr killed $r6, 14 /* CC::al */, $noreg
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; CHECK: bb.2:
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; CHECK: liveins: $lr
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; CHECK: $r0 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r1 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r2 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r3 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r4 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r5 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: bb.3:
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; CHECK: liveins: $lr, $r0, $r6, $r7
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; CHECK: $r6 = tMOVr killed $lr, 14 /* CC::al */, $noreg
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; CHECK: tBL 14 /* CC::al */, $noreg, @OUTLINED_FUNCTION_0
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; CHECK: $lr = tMOVr killed $r6, 14 /* CC::al */, $noreg
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; CHECK: bb.4:
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; CHECK: liveins: $lr
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; CHECK: $r2 = tMOVr $lr, 14 /* CC::al */, $noreg
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; CHECK: tBX_RET 14 /* CC::al */, $noreg
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bb.0:
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liveins: $lr
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$r0 = t2MOVi 1, 14, $noreg, $noreg
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$r1 = t2MOVi 1, 14, $noreg, $noreg
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$r2 = t2MOVi 1, 14, $noreg, $noreg
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$r3 = t2MOVi 1, 14, $noreg, $noreg
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$r4 = t2MOVi 1, 14, $noreg, $noreg
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$r5 = t2MOVi 1, 14, $noreg, $noreg
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bb.1:
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liveins: $lr
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$r0 = t2MOVi 1, 14, $noreg, $noreg
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$r1 = t2MOVi 1, 14, $noreg, $noreg
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$r2 = t2MOVi 1, 14, $noreg, $noreg
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$r3 = t2MOVi 1, 14, $noreg, $noreg
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$r4 = t2MOVi 1, 14, $noreg, $noreg
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$r5 = t2MOVi 1, 14, $noreg, $noreg
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bb.2:
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liveins: $lr
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$r0 = t2MOVi 1, 14, $noreg, $noreg
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$r1 = t2MOVi 1, 14, $noreg, $noreg
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$r2 = t2MOVi 1, 14, $noreg, $noreg
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$r3 = t2MOVi 1, 14, $noreg, $noreg
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$r4 = t2MOVi 1, 14, $noreg, $noreg
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$r5 = t2MOVi 1, 14, $noreg, $noreg
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bb.3:
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liveins: $lr, $r0, $r6, $r7, $r8, $r9, $r10, $r11
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$r0 = t2MOVi 1, 14, $noreg, $noreg
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$r1 = t2MOVi 1, 14, $noreg, $noreg
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$r2 = t2MOVi 1, 14, $noreg, $noreg
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$r3 = t2MOVi 1, 14, $noreg, $noreg
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$r4 = t2MOVi 1, 14, $noreg, $noreg
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$r5 = t2MOVi 1, 14, $noreg, $noreg
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bb.4:
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liveins: $lr
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$r2 = tMOVr $lr, 14, $noreg
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tBX_RET 14, $noreg
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; CHECK-LABEL: name: OUTLINED_FUNCTION_0
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; CHECK: bb.0:
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; CHECK: liveins: $lr
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; CHECK: $r0 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r1 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r2 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r3 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r4 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r5 = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: tBX_RET 14 /* CC::al */, $noreg
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; CHECK-LABEL: name: OUTLINED_FUNCTION_1
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; CHECK: bb.0:
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; CHECK: liveins: $lr
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; CHECK: $r0 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r1 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r2 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r3 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r4 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: $r5 = MOVi 1, 14 /* CC::al */, $noreg, $noreg
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; CHECK: MOVPCLR 14 /* CC::al */, $noreg
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