forked from OSchip/llvm-project
[X86][SSE] Added additional PACKUS shuffle tests
Mainly inspired by PR34773 llvm-svn: 315906
This commit is contained in:
Simon Pilgrim
parent
0d378a9eed
commit
664f2f697a
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@ -1215,6 +1215,28 @@ entry:
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ret <16 x i8> %shuffle
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}
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define <16 x i8> @shuffe_v16i8_shift_00_02_04_06_08_10_12_14_16_18_20_22_24_26_28_30(<8 x i16> %a0, <8 x i16> %a1) {
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; SSE-LABEL: shuffe_v16i8_shift_00_02_04_06_08_10_12_14_16_18_20_22_24_26_28_30:
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; SSE: # BB#0:
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; SSE-NEXT: psrlw $8, %xmm0
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; SSE-NEXT: psrlw $8, %xmm1
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; SSE-NEXT: packuswb %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: shuffe_v16i8_shift_00_02_04_06_08_10_12_14_16_18_20_22_24_26_28_30:
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; AVX: # BB#0:
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; AVX-NEXT: vpsrlw $8, %xmm0, %xmm0
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; AVX-NEXT: vpsrlw $8, %xmm1, %xmm1
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; AVX-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = lshr <8 x i16> %a0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
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%2 = lshr <8 x i16> %a1, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
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%3 = bitcast <8 x i16> %1 to <16 x i8>
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%4 = bitcast <8 x i16> %2 to <16 x i8>
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%5 = shufflevector <16 x i8> %3, <16 x i8> %4, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
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ret <16 x i8> %5
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}
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define <16 x i8> @stress_test2(<16 x i8> %s.0.0, <16 x i8> %s.0.1, <16 x i8> %s.0.2) {
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; Nothing interesting to test here. Just make sure we didn't crashe.
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; ALL-LABEL: stress_test2:
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@ -2262,6 +2262,35 @@ define <32 x i8> @shuffle_v32i8_22_22_22_22_22_22_22_22_22_22_22_22_22_22_22_22_
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ret <32 x i8> %shuffle
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}
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define <32 x i8> @shuffe_v32i8_shift_00_02_04_06_08_10_12_14_16_18_20_22_24_26_28_30_32_34_36_38_40_42_44_46_48_50_52_54_56_58_60_62(<16 x i16> %a0, <16 x i16> %a1) {
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; AVX1-LABEL: shuffe_v32i8_shift_00_02_04_06_08_10_12_14_16_18_20_22_24_26_28_30_32_34_36_38_40_42_44_46_48_50_52_54_56_58_60_62:
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; AVX1: # BB#0:
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; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
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; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
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; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
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; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
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; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
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; AVX1-NEXT: vpsrlw $8, %xmm2, %xmm2
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; AVX1-NEXT: vpsrlw $8, %xmm1, %xmm1
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; AVX1-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
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; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
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; AVX1-NEXT: retq
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;
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; AVX2OR512VL-LABEL: shuffe_v32i8_shift_00_02_04_06_08_10_12_14_16_18_20_22_24_26_28_30_32_34_36_38_40_42_44_46_48_50_52_54_56_58_60_62:
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; AVX2OR512VL: # BB#0:
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; AVX2OR512VL-NEXT: vpsrlw $8, %ymm0, %ymm0
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; AVX2OR512VL-NEXT: vpsrlw $8, %ymm1, %ymm1
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; AVX2OR512VL-NEXT: vpackuswb %ymm1, %ymm0, %ymm0
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; AVX2OR512VL-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3]
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; AVX2OR512VL-NEXT: retq
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%1 = lshr <16 x i16> %a0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
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%2 = lshr <16 x i16> %a1, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
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%3 = bitcast <16 x i16> %1 to <32 x i8>
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%4 = bitcast <16 x i16> %2 to <32 x i8>
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%5 = shufflevector <32 x i8> %3, <32 x i8> %4, <32 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30, i32 32, i32 34, i32 36, i32 38, i32 40, i32 42, i32 44, i32 46, i32 48, i32 50, i32 52, i32 54, i32 56, i32 58, i32 60, i32 62>
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ret <32 x i8> %5
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}
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define <4 x i64> @PR28136(<32 x i8> %a0, <32 x i8> %a1) {
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; AVX1-LABEL: PR28136:
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; AVX1: # BB#0:
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@ -538,3 +538,54 @@ define <64 x i8> @shuffle_v64i8_63_64_61_66_59_68_57_70_55_72_53_74_51_76_49_78_
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%shuffle = shufflevector <64 x i8> %a, <64 x i8> %b, <64 x i32> <i32 63, i32 64, i32 61, i32 66, i32 59, i32 68, i32 57, i32 70, i32 55, i32 72, i32 53, i32 74, i32 51, i32 76, i32 49, i32 78, i32 47, i32 80, i32 45, i32 82, i32 43, i32 84, i32 41, i32 86, i32 39, i32 88, i32 37, i32 90, i32 35, i32 92, i32 33, i32 94, i32 31, i32 96, i32 29, i32 98, i32 27, i32 100, i32 25, i32 102, i32 23, i32 104, i32 21, i32 106, i32 19, i32 108, i32 17, i32 110, i32 15, i32 112, i32 13, i32 114, i32 11, i32 116, i32 9, i32 118, i32 7, i32 120, i32 5, i32 122, i32 3, i32 124, i32 1, i32 126>
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ret <64 x i8> %shuffle
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}
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define <64 x i8> @shuffe_v64i8_shift_00_02_04_06_08_10_12_14_16_18_20_22_24_26_28_30_32_34_36_38_40_42_44_46_48_50_52_54_56_58_60_62_64_66_68_70_72_74_76_78_80_82_84_86_88_90_92_94_96_98_100_102_104_106_108_110_112_114_116_118_120_122_124_126(<32 x i16> %a0, <32 x i16> %a1) {
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; AVX512F-LABEL: shuffe_v64i8_shift_00_02_04_06_08_10_12_14_16_18_20_22_24_26_28_30_32_34_36_38_40_42_44_46_48_50_52_54_56_58_60_62_64_66_68_70_72_74_76_78_80_82_84_86_88_90_92_94_96_98_100_102_104_106_108_110_112_114_116_118_120_122_124_126:
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; AVX512F: # BB#0:
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; AVX512F-NEXT: vpsrlw $8, %ymm1, %ymm1
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; AVX512F-NEXT: vpsrlw $8, %ymm0, %ymm0
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; AVX512F-NEXT: vpackuswb %ymm1, %ymm0, %ymm0
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; AVX512F-NEXT: vpsrlw $8, %ymm3, %ymm1
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; AVX512F-NEXT: vpsrlw $8, %ymm2, %ymm2
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; AVX512F-NEXT: vpackuswb %ymm1, %ymm2, %ymm1
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; AVX512F-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3]
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; AVX512F-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,1,3]
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; AVX512F-NEXT: retq
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;
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; AVX512BW-LABEL: shuffe_v64i8_shift_00_02_04_06_08_10_12_14_16_18_20_22_24_26_28_30_32_34_36_38_40_42_44_46_48_50_52_54_56_58_60_62_64_66_68_70_72_74_76_78_80_82_84_86_88_90_92_94_96_98_100_102_104_106_108_110_112_114_116_118_120_122_124_126:
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; AVX512BW: # BB#0:
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; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0
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; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1
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; AVX512BW-NEXT: vextracti64x4 $1, %zmm0, %ymm2
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; AVX512BW-NEXT: vpackuswb %ymm2, %ymm0, %ymm0
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; AVX512BW-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3]
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; AVX512BW-NEXT: vextracti64x4 $1, %zmm1, %ymm2
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; AVX512BW-NEXT: vpackuswb %ymm2, %ymm1, %ymm1
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; AVX512BW-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,1,3]
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; AVX512BW-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
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; AVX512BW-NEXT: retq
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;
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; AVX512DQ-LABEL: shuffe_v64i8_shift_00_02_04_06_08_10_12_14_16_18_20_22_24_26_28_30_32_34_36_38_40_42_44_46_48_50_52_54_56_58_60_62_64_66_68_70_72_74_76_78_80_82_84_86_88_90_92_94_96_98_100_102_104_106_108_110_112_114_116_118_120_122_124_126:
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; AVX512DQ: # BB#0:
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; AVX512DQ-NEXT: vpsrlw $8, %ymm1, %ymm1
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; AVX512DQ-NEXT: vpsrlw $8, %ymm0, %ymm0
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; AVX512DQ-NEXT: vpackuswb %ymm1, %ymm0, %ymm0
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; AVX512DQ-NEXT: vpsrlw $8, %ymm3, %ymm1
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; AVX512DQ-NEXT: vpsrlw $8, %ymm2, %ymm2
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; AVX512DQ-NEXT: vpackuswb %ymm1, %ymm2, %ymm1
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; AVX512DQ-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,1,3]
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; AVX512DQ-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,1,3]
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; AVX512DQ-NEXT: retq
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;
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; AVX512VBMI-LABEL: shuffe_v64i8_shift_00_02_04_06_08_10_12_14_16_18_20_22_24_26_28_30_32_34_36_38_40_42_44_46_48_50_52_54_56_58_60_62_64_66_68_70_72_74_76_78_80_82_84_86_88_90_92_94_96_98_100_102_104_106_108_110_112_114_116_118_120_122_124_126:
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; AVX512VBMI: # BB#0:
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; AVX512VBMI-NEXT: vmovdqa64 {{.*#+}} zmm2 = [1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31,33,35,37,39,41,43,45,47,49,51,53,55,57,59,61,63,65,67,69,71,73,75,77,79,81,83,85,87,89,91,93,95,97,99,101,103,105,107,109,111,113,115,117,119,121,123,125,127]
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; AVX512VBMI-NEXT: vpermt2b %zmm1, %zmm2, %zmm0
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; AVX512VBMI-NEXT: retq
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%1 = lshr <32 x i16> %a0, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
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%2 = lshr <32 x i16> %a1, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
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%3 = bitcast <32 x i16> %1 to <64 x i8>
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%4 = bitcast <32 x i16> %2 to <64 x i8>
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%5 = shufflevector <64 x i8> %3, <64 x i8> %4, <64 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30, i32 32, i32 34, i32 36, i32 38, i32 40, i32 42, i32 44, i32 46, i32 48, i32 50, i32 52, i32 54, i32 56, i32 58, i32 60, i32 62, i32 64, i32 66, i32 68, i32 70, i32 72, i32 74, i32 76, i32 78, i32 80, i32 82, i32 84, i32 86, i32 88, i32 90, i32 92, i32 94, i32 96, i32 98, i32 100, i32 102, i32 104, i32 106, i32 108, i32 110, i32 112, i32 114, i32 116, i32 118, i32 120, i32 122, i32 124, i32 126>
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ret <64 x i8> %5
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}
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