maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[NVPTX] Fix bug with int_nvvm_rotate_b64 when operand immediate 

Need to subract from 64, not 32.

Reviewed By: tra

Differential Revision: https://reviews.llvm.org/D119639
This commit is contained in:
Dmitry Vassiliev 2022-02-15 01:23:11 +03:00
parent 37f422f4ac
commit 6645bfa8f5
2 changed files with 26 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
View File

@ -2473,7 +2473,7 @@ def : Pat<(int_nvvm_rotate_right_b64 Int64Regs:$src, Int32Regs:$amt),
// SW version of rotate 64 // SW version of rotate 64
def : Pat<(int_nvvm_rotate_b64 Int64Regs:$src, (i32 imm:$amt)), def : Pat<(int_nvvm_rotate_b64 Int64Regs:$src, (i32 imm:$amt)),
(ROT64imm_sw Int64Regs:$src, imm:$amt, (SUB_FRM_32 node:$amt))>, (ROT64imm_sw Int64Regs:$src, imm:$amt, (SUB_FRM_64 node:$amt))>,
Requires<[noHWROT32]>; Requires<[noHWROT32]>;
def : Pat<(int_nvvm_rotate_b64 Int64Regs:$src, Int32Regs:$amt), def : Pat<(int_nvvm_rotate_b64 Int64Regs:$src, Int32Regs:$amt),
(ROTL64reg_sw Int64Regs:$src, Int32Regs:$amt)>, (ROTL64reg_sw Int64Regs:$src, Int32Regs:$amt)>,

25
llvm/test/CodeGen/NVPTX/rotate_64.ll Normal file
View File

@ -0,0 +1,25 @@
; RUN: llc < %s -march=nvptx | FileCheck %s
declare i64 @llvm.nvvm.rotate.b64(i64, i32)
declare i64 @llvm.nvvm.rotate.right.b64(i64, i32)
; CHECK: rotate64
define i64 @rotate64(i64 %a, i32 %b) {
; CHECK: shl.b64 [[LHS:%.*]], [[RD1:%.*]], 3;
; CHECK: shr.b64 [[RHS:%.*]], [[RD1]], 61;
; CHECK: add.u64 [[RD2:%.*]], [[LHS]], [[RHS]];
; CHECK: ret
%val = tail call i64 @llvm.nvvm.rotate.b64(i64 %a, i32 3)
ret i64 %val
}
; CHECK: rotateright64
define i64 @rotateright64(i64 %a, i32 %b) {
; CHECK: shl.b64 [[LHS:%.*]], [[RD1:%.*]], 61;
; CHECK: shr.b64 [[RHS:%.*]], [[RD1]], 3;
; CHECK: add.u64 [[RD2:%.*]], [[LHS]], [[RHS]];
; CHECK: ret
%val = tail call i64 @llvm.nvvm.rotate.right.b64(i64 %a, i32 3)
ret i64 %val
}