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[AMDGPU] Update AMD GPU documentation 

- AMDGPUUsage.rst: Correct AMD GPU DWARF address space table address
  sizes which are in bits and not bytes.

- clang/.../Options.td: Improve description of AMD GPU options.

- Re-generate ClangComamndLineReference.rst from clang/.../Options.td .

Differential Revision: https://reviews.llvm.org/D90364
This commit is contained in:
Tony 2020-10-28 22:20:51 +00:00
parent 8aaafa06b2
commit 661797bd76
3 changed files with 53 additions and 42 deletions
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48
clang/docs/ClangCommandLineReference.rst
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@ -1641,6 +1641,10 @@ Sets various macros to claim compatibility with the given GCC version (default i
Allow device side init function in HIP Allow device side init function in HIP
.. option:: -fgpu-defer-diag, -fno-gpu-defer-diag
Defer host/device related diagnostic messages for CUDA/HIP
.. option:: -fgpu-rdc, -fcuda-rdc, -fno-gpu-rdc .. option:: -fgpu-rdc, -fcuda-rdc, -fno-gpu-rdc
Generate relocatable device code, also known as separate compilation mode Generate relocatable device code, also known as separate compilation mode
@ -2655,6 +2659,10 @@ Align selected branches (fused, jcc, jmp) within 32-byte boundary
.. option:: -mcmodel=<arg>, -mcmodel=medany (equivalent to -mcmodel=medium), -mcmodel=medlow (equivalent to -mcmodel=small) .. option:: -mcmodel=<arg>, -mcmodel=medany (equivalent to -mcmodel=medium), -mcmodel=medlow (equivalent to -mcmodel=small)
.. option:: -mcode-object-v3, -mno-code-object-v3
Legacy option to specify code object ABI V2 (-mnocode-object-v3) or V3 (-mcode-object-v3) (AMDGPU only)
.. option:: -mconsole<arg> .. option:: -mconsole<arg>
.. program:: clang1 .. program:: clang1
@ -2831,6 +2839,18 @@ Enable stack probes
Set the stack probe size Set the stack probe size
.. option:: -mstack-protector-guard-offset=<arg>
Use the given offset for addressing the stack-protector guard
.. option:: -mstack-protector-guard-reg=<arg>
Use the given reg for addressing the stack-protector guard
.. option:: -mstack-protector-guard=<arg>
Use the given guard (global, tls) for addressing the stack-protector guard
.. option:: -mstackrealign, -mno-stackrealign .. option:: -mstackrealign, -mno-stackrealign
Force realign the stack at entry to every function Force realign the stack at entry to every function
@ -2859,7 +2879,7 @@ Specify bit size of immediate TLS offsets (AArch64 ELF only): 12 (for 4KB) \| 24
.. option:: -mtune=<arg> .. option:: -mtune=<arg>
.. program:: clang .. program:: clang
Only supported on X86. Otherwise accepted for compatibility with GCC. Only supported on X86 and RISC-V. Otherwise accepted for compatibility with GCC.
.. option:: -mtvos-version-min=<arg>, -mappletvos-version-min=<arg> .. option:: -mtvos-version-min=<arg>, -mappletvos-version-min=<arg>
@ -2873,7 +2893,7 @@ Only supported on X86. Otherwise accepted for compatibility with GCC.
.. option:: -mwavefrontsize64, -mno-wavefrontsize64 .. option:: -mwavefrontsize64, -mno-wavefrontsize64
Wavefront size 64 is used Specify wavefront size 64 mode (AMDGPU only)
.. option:: -mwindows<arg> .. option:: -mwindows<arg>
@ -2935,28 +2955,28 @@ Specify the size in bits of an SVE vector register. Defaults to the vector lengt
AMDGPU AMDGPU
------ ------
.. option:: -mcode-object-v3, -mno-code-object-v3
Legacy option to specify code object v3 (AMDGPU only)
.. option:: -mcumode, -mno-cumode .. option:: -mcumode, -mno-cumode
CU wavefront execution mode is used (AMDGPU only) Specify CU (-mcumode) or WGP (-mno-cumode) wavefront execution mode (AMDGPU only)
.. option:: -msram-ecc, -mno-sram-ecc .. option:: -msram-ecc, -mno-sram-ecc
Enable SRAM ECC (AMDGPU only) Specify SRAM ECC mode (AMDGPU only)
.. option:: -mxnack, -mno-xnack .. option:: -mxnack, -mno-xnack
Enable XNACK (AMDGPU only) Specify XNACK mode (AMDGPU only)
ARM ARM
--- ---
.. option:: -fAAPCSBitfieldLoad .. option:: -faapcs-bitfield-load
Follows the AAPCS standard that all volatile bit-field write generates at least one load. (ARM only). Follows the AAPCS standard that all volatile bit-field write generates at least one load. (ARM only).
.. option:: -faapcs-bitfield-width, -fno-aapcs-bitfield-width
Follow the AAPCS standard requirement stating that volatile bit-field width is dictated by the field container type. (ARM only).
.. option:: -ffixed-r9 .. option:: -ffixed-r9
Reserve the r9 register (ARM only) Reserve the r9 register (ARM only)
@ -3490,13 +3510,7 @@ Set DWARF fission mode to either 'split' or 'single'
.. option:: -gstrict-dwarf, -gno-strict-dwarf .. option:: -gstrict-dwarf, -gno-strict-dwarf
.. option:: -gz .. option:: -gz=<arg>, -gz (equivalent to -gz=zlib)
DWARF debug sections compression type
.. program:: clang1
.. option:: -gz=<arg>
.. program:: clang
DWARF debug sections compression type DWARF debug sections compression type

35
clang/include/clang/Driver/Options.td
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@ -2468,28 +2468,25 @@ def mexec_model_EQ : Joined<["-"], "mexec-model=">, Group<m_wasm_Features_Driver
HelpText<"Execution model (WebAssembly only)">; HelpText<"Execution model (WebAssembly only)">;
def mcode_object_v3_legacy : Flag<["-"], "mcode-object-v3">, Group<m_Group>, def mcode_object_v3_legacy : Flag<["-"], "mcode-object-v3">, Group<m_Group>,
HelpText<"Legacy option to specify code object v3 (AMDGPU only)">; HelpText<"Legacy option to specify code object ABI V2 (-mnocode-object-v3) or V3 (-mcode-object-v3) (AMDGPU only)">;
def mno_code_object_v3_legacy : Flag<["-"], "mno-code-object-v3">, Group<m_Group>, def mno_code_object_v3_legacy : Flag<["-"], "mno-code-object-v3">, Group<m_Group>;
HelpText<"Legacy option to specify code object v2 (AMDGPU only)">;
def mxnack : Flag<["-"], "mxnack">, Group<m_amdgpu_Features_Group>,
HelpText<"Enable XNACK (AMDGPU only)">;
def mno_xnack : Flag<["-"], "mno-xnack">, Group<m_amdgpu_Features_Group>,
HelpText<"Disable XNACK (AMDGPU only)">;
def msram_ecc : Flag<["-"], "msram-ecc">, Group<m_amdgpu_Features_Group>,
HelpText<"Enable SRAM ECC (AMDGPU only)">;
def mno_sram_ecc : Flag<["-"], "mno-sram-ecc">, Group<m_amdgpu_Features_Group>,
HelpText<"Disable SRAM ECC (AMDGPU only)">;
def mcumode : Flag<["-"], "mcumode">, Group<m_amdgpu_Features_Group>, def mcumode : Flag<["-"], "mcumode">, Group<m_amdgpu_Features_Group>,
HelpText<"CU wavefront execution mode is used (AMDGPU only)">; HelpText<"Specify CU (-mcumode) or WGP (-mno-cumode) wavefront execution mode (AMDGPU only)">;
def mno_cumode : Flag<["-"], "mno-cumode">, Group<m_amdgpu_Features_Group>, def mno_cumode : Flag<["-"], "mno-cumode">, Group<m_amdgpu_Features_Group>;
HelpText<"WGP wavefront execution mode is used (AMDGPU only)">;
def mwavefrontsize64 : Flag<["-"], "mwavefrontsize64">, def msram_ecc : Flag<["-"], "msram-ecc">, Group<m_amdgpu_Features_Group>,
Group<m_Group>, HelpText<"Wavefront size 64 is used">; HelpText<"Specify SRAM ECC mode (AMDGPU only)">;
def mno_wavefrontsize64 : Flag<["-"], "mno-wavefrontsize64">, def mno_sram_ecc : Flag<["-"], "mno-sram-ecc">, Group<m_amdgpu_Features_Group>;
Group<m_Group>, HelpText<"Wavefront size 32 is used">;
def mwavefrontsize64 : Flag<["-"], "mwavefrontsize64">, Group<m_Group>,
HelpText<"Specify wavefront size 64 mode (AMDGPU only)">;
def mno_wavefrontsize64 : Flag<["-"], "mno-wavefrontsize64">, Group<m_Group>,
HelpText<"Specify wavefront size 32 mode (AMDGPU only)">;
def mxnack : Flag<["-"], "mxnack">, Group<m_amdgpu_Features_Group>,
HelpText<"Specify XNACK mode (AMDGPU only)">;
def mno_xnack : Flag<["-"], "mno-xnack">, Group<m_amdgpu_Features_Group>;
def faltivec : Flag<["-"], "faltivec">, Group<f_Group>, Flags<[DriverOption]>; def faltivec : Flag<["-"], "faltivec">, Group<f_Group>, Flags<[DriverOption]>;
def fno_altivec : Flag<["-"], "fno-altivec">, Group<f_Group>, Flags<[DriverOption]>; def fno_altivec : Flag<["-"], "fno-altivec">, Group<f_Group>, Flags<[DriverOption]>;

12
llvm/docs/AMDGPUUsage.rst
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@ -1411,13 +1411,13 @@ The DWARF address space mapping used for AMDGPU is defined in
address address address address
space space space space
======================================= ===== ======= ======== ================= ======================= ======================================= ===== ======= ======== ================= =======================
``DW_ASPACE_none`` 0x00 8 4 Global *default address space* ``DW_ASPACE_none`` 0x00 64 32 Global *default address space*
``DW_ASPACE_AMDGPU_generic`` 0x01 8 4 Generic (Flat) ``DW_ASPACE_AMDGPU_generic`` 0x01 64 32 Generic (Flat)
``DW_ASPACE_AMDGPU_region`` 0x02 4 4 Region (GDS) ``DW_ASPACE_AMDGPU_region`` 0x02 32 32 Region (GDS)
``DW_ASPACE_AMDGPU_local`` 0x03 4 4 Local (group/LDS) ``DW_ASPACE_AMDGPU_local`` 0x03 32 32 Local (group/LDS)
*Reserved* 0x04 *Reserved* 0x04
``DW_ASPACE_AMDGPU_private_lane`` 0x05 4 4 Private (Scratch) *focused lane* ``DW_ASPACE_AMDGPU_private_lane`` 0x05 32 32 Private (Scratch) *focused lane*
``DW_ASPACE_AMDGPU_private_wave`` 0x06 4 4 Private (Scratch) *unswizzled wavefront* ``DW_ASPACE_AMDGPU_private_wave`` 0x06 32 32 Private (Scratch) *unswizzled wavefront*
======================================= ===== ======= ======== ================= ======================= ======================================= ===== ======= ======== ================= =======================
See :ref:`amdgpu-address-spaces` for information on the AMDGPU address spaces See :ref:`amdgpu-address-spaces` for information on the AMDGPU address spaces