forked from OSchip/llvm-project
Use ADDC if it is valid at any smaller size. fixes test/Codegen/Generic/i128-addsub.ll on x86
llvm-svn: 57247
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@ -6441,7 +6441,20 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
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LoOps[1] = RHSL;
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HiOps[0] = LHSH;
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HiOps[1] = RHSH;
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if(TLI.isOperationLegal(ISD::ADDC, NVT)) {
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//cascaded check to see if any smaller size has a a carry flag.
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unsigned OpV = Node->getOpcode() == ISD::ADD ? ISD::ADDC : ISD::SUBC;
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bool hasCarry = false;
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if (NVT == MVT::i64)
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hasCarry |= TLI.isOperationLegal(OpV, MVT::i32)
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| TLI.isOperationLegal(OpV, MVT::i16)
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| TLI.isOperationLegal(OpV, MVT::i8);
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if (NVT == MVT::i32)
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hasCarry |= TLI.isOperationLegal(OpV, MVT::i16)
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| TLI.isOperationLegal(OpV, MVT::i8);
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if (NVT == MVT::i16)
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hasCarry |= TLI.isOperationLegal(OpV, MVT::i8);
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if(hasCarry) {
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if (Node->getOpcode() == ISD::ADD) {
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Lo = DAG.getNode(ISD::ADDC, VTList, LoOps, 2);
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HiOps[2] = Lo.getValue(1);
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@ -6456,11 +6469,13 @@ void SelectionDAGLegalize::ExpandOp(SDValue Op, SDValue &Lo, SDValue &Hi){
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if (Node->getOpcode() == ISD::ADD) {
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Lo = DAG.getNode(ISD::ADD, VTList, LoOps, 2);
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Hi = DAG.getNode(ISD::ADD, VTList, HiOps, 2);
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SDValue Cmp1 = DAG.getSetCC(NVT, Lo, LoOps[0], ISD::SETULT);
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SDValue Cmp1 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
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Lo, LoOps[0], ISD::SETULT);
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SDValue Carry1 = DAG.getNode(ISD::SELECT, NVT, Cmp1,
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DAG.getConstant(1, NVT),
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DAG.getConstant(0, NVT));
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SDValue Cmp2 = DAG.getSetCC(NVT, Lo, LoOps[1], ISD::SETULT);
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SDValue Cmp2 = DAG.getSetCC(TLI.getSetCCResultType(Lo),
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Lo, LoOps[1], ISD::SETULT);
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SDValue Carry2 = DAG.getNode(ISD::SELECT, NVT, Cmp2,
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DAG.getConstant(1, NVT),
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Carry1);
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