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ARM optional destination operand variants for VEXT instructions. 

llvm-svn: 146114
This commit is contained in:
Jim Grosbach 2011-12-08 00:43:47 +00:00
parent 5ff64c7141
commit 6600f520b0
2 changed files with 32 additions and 0 deletions
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17
llvm/lib/Target/ARM/ARMInstrNEON.td
View File

@ -5491,3 +5491,20 @@ def : NEONInstAlias<"vclt${p}.u32 $Qd, $Qn, $Qm",
(VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
def : NEONInstAlias<"vclt${p}.f32 $Qd, $Qn, $Qm",
(VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
// Two-operand variants for VEXT
def : NEONInstAlias<"vext${p}.8 $Vdn, $Vm, $imm",
(VEXTd8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_7:$imm, pred:$p)>;
def : NEONInstAlias<"vext${p}.16 $Vdn, $Vm, $imm",
(VEXTd16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_3:$imm, pred:$p)>;
def : NEONInstAlias<"vext${p}.32 $Vdn, $Vm, $imm",
(VEXTd32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_1:$imm, pred:$p)>;
def : NEONInstAlias<"vext${p}.8 $Vdn, $Vm, $imm",
(VEXTq8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_15:$imm, pred:$p)>;
def : NEONInstAlias<"vext${p}.16 $Vdn, $Vm, $imm",
(VEXTq16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_7:$imm, pred:$p)>;
def : NEONInstAlias<"vext${p}.32 $Vdn, $Vm, $imm",
(VEXTq32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_3:$imm, pred:$p)>;
def : NEONInstAlias<"vext${p}.64 $Vdn, $Vm, $imm",
(VEXTq64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_1:$imm, pred:$p)>;

15
llvm/test/MC/ARM/neon-shuffle-encoding.s
View File

@ -7,6 +7,14 @@
vext.16 d16, d17, d16, #3
vext.32 q8, q9, q8, #3
vext.8 d17, d16, #3
vext.8 d7, d11, #5
vext.8 q3, q8, #3
vext.8 q9, q4, #7
vext.16 d1, d26, #3
vext.32 q5, q8, #3
@ CHECK: vext.8 d16, d17, d16, #3 @ encoding: [0xa0,0x03,0xf1,0xf2]
@ CHECK: vext.8 d16, d17, d16, #5 @ encoding: [0xa0,0x05,0xf1,0xf2]
@ CHECK: vext.8 q8, q9, q8, #3 @ encoding: [0xe0,0x03,0xf2,0xf2]
@ -14,6 +22,13 @@
@ CHECK: vext.16 d16, d17, d16, #3 @ encoding: [0xa0,0x06,0xf1,0xf2]
@ CHECK: vext.32 q8, q9, q8, #3 @ encoding: [0xe0,0x0c,0xf2,0xf2]
@ CHECK: vext.8 d17, d17, d16, #3 @ encoding: [0xa0,0x13,0xf1,0xf2]
@ CHECK: vext.8 d7, d7, d11, #5 @ encoding: [0x0b,0x75,0xb7,0xf2]
@ CHECK: vext.8 q3, q3, q8, #3 @ encoding: [0x60,0x63,0xb6,0xf2]
@ CHECK: vext.8 q9, q9, q4, #7 @ encoding: [0xc8,0x27,0xf2,0xf2]
@ CHECK: vext.16 d1, d1, d26, #3 @ encoding: [0x2a,0x16,0xb1,0xf2]
@ CHECK: vext.32 q5, q5, q8, #3 @ encoding: [0x60,0xac,0xba,0xf2]
vtrn.8 d17, d16
vtrn.16 d17, d16