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[AMDGPU] Remove selectSGPRVectorRegClassID. NFC. 

This was yet another function that had to be updated whenever you added
a new register class. Remove it by refactoring its only caller to use
standard helper functions from SIRegisterInfo.

Differential Revision: https://reviews.llvm.org/D78557
This commit is contained in:
Jay Foad 2020-04-21 13:34:23 +01:00
parent 497c76e96d
commit 658f33dcea
3 changed files with 12 additions and 27 deletions
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26
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
View File

@ -647,29 +647,6 @@ MachineSDNode *AMDGPUDAGToDAGISel::buildSMovImm64(SDLoc &DL, uint64_t Imm,
return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, VT, Ops);
}
static unsigned selectSGPRVectorRegClassID(unsigned NumVectorElts) {
switch (NumVectorElts) {
case 1:
return AMDGPU::SReg_32RegClassID;
case 2:
return AMDGPU::SReg_64RegClassID;
case 3:
return AMDGPU::SGPR_96RegClassID;
case 4:
return AMDGPU::SGPR_128RegClassID;
case 5:
return AMDGPU::SGPR_160RegClassID;
case 8:
return AMDGPU::SReg_256RegClassID;
case 16:
return AMDGPU::SReg_512RegClassID;
case 32:
return AMDGPU::SReg_1024RegClassID;
}
llvm_unreachable("invalid vector size");
}
void AMDGPUDAGToDAGISel::SelectBuildVector(SDNode *N, unsigned RegClassID) {
EVT VT = N->getValueType(0);
unsigned NumVectorElts = VT.getVectorNumElements();
@ -797,7 +774,8 @@ void AMDGPUDAGToDAGISel::Select(SDNode *N) {
}
assert(VT.getVectorElementType().bitsEq(MVT::i32));
unsigned RegClassID = selectSGPRVectorRegClassID(NumVectorElts);
unsigned RegClassID =
SIRegisterInfo::getSGPRClassForBitWidth(NumVectorElts * 32)->getID();
SelectBuildVector(N, RegClassID);
return;
}

9
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
View File

@ -1274,7 +1274,8 @@ StringRef SIRegisterInfo::getRegAsmName(MCRegister Reg) const {
return AMDGPUInstPrinter::getRegisterName(Reg);
}
static const TargetRegisterClass *getVGPRClassForBitWidth(unsigned BitWidth) {
const TargetRegisterClass *
SIRegisterInfo::getVGPRClassForBitWidth(unsigned BitWidth) {
switch (BitWidth) {
case 1:
return &AMDGPU::VReg_1RegClass;
@ -1301,7 +1302,8 @@ static const TargetRegisterClass *getVGPRClassForBitWidth(unsigned BitWidth) {
}
}
static const TargetRegisterClass *getAGPRClassForBitWidth(unsigned BitWidth) {
const TargetRegisterClass *
SIRegisterInfo::getAGPRClassForBitWidth(unsigned BitWidth) {
switch (BitWidth) {
case 32:
return &AMDGPU::AGPR_32RegClass;
@ -1318,7 +1320,8 @@ static const TargetRegisterClass *getAGPRClassForBitWidth(unsigned BitWidth) {
}
}
static const TargetRegisterClass *getSGPRClassForBitWidth(unsigned BitWidth) {
const TargetRegisterClass *
SIRegisterInfo::getSGPRClassForBitWidth(unsigned BitWidth) {
switch (BitWidth) {
case 16:
return &AMDGPU::SGPR_LO16RegClass;

4
llvm/lib/Target/AMDGPU/SIRegisterInfo.h
View File

@ -116,6 +116,10 @@ public:
return getEncodingValue(Reg) & 0xff;
}
static const TargetRegisterClass *getVGPRClassForBitWidth(unsigned BitWidth);
static const TargetRegisterClass *getAGPRClassForBitWidth(unsigned BitWidth);
static const TargetRegisterClass *getSGPRClassForBitWidth(unsigned BitWidth);
/// Return the 'base' register class for this register.
/// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
const TargetRegisterClass *getPhysRegClass(MCRegister Reg) const;