forked from OSchip/llvm-project
parent
17ba6becaa
commit
65825cd7c5
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@ -19,7 +19,7 @@ foreach SIZE = [2, 4, 8, 16, 32] in
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def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
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def LaneIdx#SIZE : ImmLeaf<i32, "return 0 <= Imm && Imm < "#SIZE#";">;
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multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> {
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multiclass ConstVec<ValueType vec_t, dag ops, dag pat, string args> {
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let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in
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let isMoveImm = 1, isReMaterializable = 1 in
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defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops,
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defm CONST_V128_#vec_t : SIMD_I<(outs V128:$dst), ops, (outs), ops,
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[(set V128:$dst, (vec_t pat))],
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[(set V128:$dst, (vec_t pat))],
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"v128.const\t$dst, "#args,
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"v128.const\t$dst, "#args,
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