forked from OSchip/llvm-project
AMDGPU: Fix verifier error with kill intrinsic
Don't create a terminator in the middle of the block. We should probably get rid of this intrinsic. llvm-svn: 275203
This commit is contained in:
Matt Arsenault
parent
b9f8e29290
commit
657f871a4e
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@ -76,7 +76,7 @@ private:
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bool shouldSkip(MachineBasicBlock *From, MachineBasicBlock *To);
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void Skip(MachineInstr &From, MachineOperand &To);
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void SkipIfDead(MachineInstr &MI);
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bool skipIfDead(MachineInstr &MI);
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void If(MachineInstr &MI);
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void Else(MachineInstr &MI, bool ExecModified);
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@ -89,12 +89,16 @@ private:
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void Kill(MachineInstr &MI);
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void Branch(MachineInstr &MI);
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void splitBlockLiveIns(const MachineBasicBlock &MBB,
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const MachineInstr &MI,
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MachineBasicBlock &LoopBB,
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MachineBasicBlock &RemainderBB,
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unsigned SaveReg,
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const MachineOperand &IdxReg);
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std::pair<MachineBasicBlock *, MachineBasicBlock *>
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splitBlock(MachineBasicBlock &MBB, MachineBasicBlock::iterator I);
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void splitLoadM0BlockLiveIns(LivePhysRegs &RemainderLiveRegs,
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const MachineRegisterInfo &MRI,
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const MachineInstr &MI,
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MachineBasicBlock &LoopBB,
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MachineBasicBlock &RemainderBB,
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unsigned SaveReg,
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const MachineOperand &IdxReg);
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void emitLoadM0FromVGPRLoop(MachineBasicBlock &LoopBB, DebugLoc DL,
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MachineInstr *MovRel,
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@ -171,7 +175,19 @@ bool SILowerControlFlow::shouldSkip(MachineBasicBlock *From,
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I->getOpcode() == AMDGPU::S_CBRANCH_VCCZ)
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return true;
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if (++NumInstr >= SkipThreshold)
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if (I->isInlineAsm()) {
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const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
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const char *AsmStr = I->getOperand(0).getSymbolName();
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// inlineasm length estimate is number of bytes assuming the longest
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// instruction.
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uint64_t MaxAsmSize = TII->getInlineAsmLength(AsmStr, *MAI);
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NumInstr += MaxAsmSize / MAI->getMaxInstLength();
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} else {
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++NumInstr;
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}
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if (NumInstr >= SkipThreshold)
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return true;
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}
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}
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@ -189,36 +205,55 @@ void SILowerControlFlow::Skip(MachineInstr &From, MachineOperand &To) {
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.addOperand(To);
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}
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void SILowerControlFlow::SkipIfDead(MachineInstr &MI) {
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bool SILowerControlFlow::skipIfDead(MachineInstr &MI) {
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MachineBasicBlock &MBB = *MI.getParent();
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DebugLoc DL = MI.getDebugLoc();
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if (MBB.getParent()->getFunction()->getCallingConv() != CallingConv::AMDGPU_PS ||
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!shouldSkip(&MBB, &MBB.getParent()->back()))
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return;
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return false;
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MachineBasicBlock::iterator Insert = &MI;
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++Insert;
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LivePhysRegs RemainderLiveRegs(TRI);
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RemainderLiveRegs.addLiveOuts(MBB);
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MachineBasicBlock *SkipBB;
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MachineBasicBlock *RemainderBB;
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std::tie(SkipBB, RemainderBB) = splitBlock(MBB, MI.getIterator());
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const DebugLoc &DL = MI.getDebugLoc();
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// If the exec mask is non-zero, skip the next two instructions
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BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
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.addImm(3);
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BuildMI(&MBB, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
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.addMBB(RemainderBB);
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MBB.addSuccessor(RemainderBB);
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MachineBasicBlock::iterator Insert = SkipBB->begin();
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// Exec mask is zero: Export to NULL target...
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BuildMI(MBB, Insert, DL, TII->get(AMDGPU::EXP))
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.addImm(0)
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.addImm(0x09) // V_008DFC_SQ_EXP_NULL
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.addImm(0)
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.addImm(1)
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.addImm(1)
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.addReg(AMDGPU::VGPR0)
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.addReg(AMDGPU::VGPR0)
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.addReg(AMDGPU::VGPR0)
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.addReg(AMDGPU::VGPR0);
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BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::EXP))
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.addImm(0)
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.addImm(0x09) // V_008DFC_SQ_EXP_NULL
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.addImm(0)
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.addImm(1)
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.addImm(1)
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.addReg(AMDGPU::VGPR0, RegState::Undef)
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.addReg(AMDGPU::VGPR0, RegState::Undef)
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.addReg(AMDGPU::VGPR0, RegState::Undef)
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.addReg(AMDGPU::VGPR0, RegState::Undef);
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// ... and terminate wavefront
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BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
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// ... and terminate wavefront.
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BuildMI(*SkipBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
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for (const MachineInstr &Inst : reverse(*RemainderBB))
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RemainderLiveRegs.stepBackward(Inst);
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const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
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for (unsigned Reg : RemainderLiveRegs) {
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if (MRI.isAllocatable(Reg))
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RemainderBB->addLiveIn(Reg);
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}
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return true;
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}
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void SILowerControlFlow::If(MachineInstr &MI) {
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@ -386,20 +421,13 @@ void SILowerControlFlow::Kill(MachineInstr &MI) {
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}
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// All currently live registers must remain so in the remainder block.
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void SILowerControlFlow::splitBlockLiveIns(const MachineBasicBlock &MBB,
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const MachineInstr &MI,
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MachineBasicBlock &LoopBB,
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MachineBasicBlock &RemainderBB,
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unsigned SaveReg,
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const MachineOperand &IdxReg) {
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LivePhysRegs RemainderLiveRegs(TRI);
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RemainderLiveRegs.addLiveOuts(MBB);
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for (MachineBasicBlock::const_reverse_iterator I = MBB.rbegin(), E(&MI);
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I != E; ++I) {
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RemainderLiveRegs.stepBackward(*I);
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}
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void SILowerControlFlow::splitLoadM0BlockLiveIns(LivePhysRegs &RemainderLiveRegs,
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const MachineRegisterInfo &MRI,
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const MachineInstr &MI,
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MachineBasicBlock &LoopBB,
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MachineBasicBlock &RemainderBB,
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unsigned SaveReg,
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const MachineOperand &IdxReg) {
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// Add reg defined in loop body.
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RemainderLiveRegs.addReg(SaveReg);
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@ -410,13 +438,11 @@ void SILowerControlFlow::splitBlockLiveIns(const MachineBasicBlock &MBB,
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}
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}
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const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
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for (unsigned Reg : RemainderLiveRegs) {
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if (MRI.isAllocatable(Reg))
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RemainderBB.addLiveIn(Reg);
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}
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const MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::src);
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if (!Src->isUndef())
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LoopBB.addLiveIn(Src->getReg());
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@ -469,6 +495,30 @@ void SILowerControlFlow::emitLoadM0FromVGPRLoop(MachineBasicBlock &LoopBB,
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.addMBB(&LoopBB);
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}
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std::pair<MachineBasicBlock *, MachineBasicBlock *>
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SILowerControlFlow::splitBlock(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) {
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MachineFunction *MF = MBB.getParent();
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// To insert the loop we need to split the block. Move everything after this
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// point to a new block, and insert a new empty block between the two.
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MachineBasicBlock *LoopBB = MF->CreateMachineBasicBlock();
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MachineBasicBlock *RemainderBB = MF->CreateMachineBasicBlock();
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MachineFunction::iterator MBBI(MBB);
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++MBBI;
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MF->insert(MBBI, LoopBB);
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MF->insert(MBBI, RemainderBB);
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// Move the rest of the block into a new block.
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RemainderBB->transferSuccessors(&MBB);
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RemainderBB->splice(RemainderBB->begin(), &MBB, I, MBB.end());
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MBB.addSuccessor(LoopBB);
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return std::make_pair(LoopBB, RemainderBB);
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}
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// Returns true if a new block was inserted.
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bool SILowerControlFlow::loadM0(MachineInstr &MI, MachineInstr *MovRel, int Offset) {
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MachineBasicBlock &MBB = *MI.getParent();
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@ -492,7 +542,6 @@ bool SILowerControlFlow::loadM0(MachineInstr &MI, MachineInstr *MovRel, int Offs
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return false;
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}
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MachineFunction &MF = *MBB.getParent();
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MachineOperand *SaveOp = TII->getNamedOperand(MI, AMDGPU::OpName::sdst);
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SaveOp->setIsDead(false);
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unsigned Save = SaveOp->getReg();
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@ -505,25 +554,24 @@ bool SILowerControlFlow::loadM0(MachineInstr &MI, MachineInstr *MovRel, int Offs
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BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B64), Save)
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.addReg(AMDGPU::EXEC);
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// To insert the loop we need to split the block. Move everything after this
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// point to a new block, and insert a new empty block between the two.
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MachineBasicBlock *LoopBB = MF.CreateMachineBasicBlock();
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MachineBasicBlock *RemainderBB = MF.CreateMachineBasicBlock();
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MachineFunction::iterator MBBI(MBB);
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++MBBI;
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LivePhysRegs RemainderLiveRegs(TRI);
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MF.insert(MBBI, LoopBB);
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MF.insert(MBBI, RemainderBB);
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RemainderLiveRegs.addLiveOuts(MBB);
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LoopBB->addSuccessor(LoopBB);
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MachineBasicBlock *LoopBB;
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MachineBasicBlock *RemainderBB;
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std::tie(LoopBB, RemainderBB) = splitBlock(MBB, I);
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for (const MachineInstr &Inst : reverse(*RemainderBB))
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RemainderLiveRegs.stepBackward(Inst);
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MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
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LoopBB->addSuccessor(RemainderBB);
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LoopBB->addSuccessor(LoopBB);
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splitBlockLiveIns(MBB, MI, *LoopBB, *RemainderBB, Save, *Idx);
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// Move the rest of the block into a new block.
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RemainderBB->transferSuccessors(&MBB);
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RemainderBB->splice(RemainderBB->begin(), &MBB, I, MBB.end());
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MBB.addSuccessor(LoopBB);
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splitLoadM0BlockLiveIns(RemainderLiveRegs, MRI, MI, *LoopBB,
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*RemainderBB, Save, *Idx);
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emitLoadM0FromVGPRLoop(*LoopBB, DL, MovRel, *Idx, Offset);
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@ -695,16 +743,25 @@ bool SILowerControlFlow::runOnMachineFunction(MachineFunction &MF) {
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case AMDGPU::SI_END_CF:
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if (--Depth == 0 && HaveKill) {
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SkipIfDead(MI);
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HaveKill = false;
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if (skipIfDead(MI)) {
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NextBB = std::next(BI);
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BE = MF.end();
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Next = MBB.end();
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}
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}
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EndCf(MI);
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break;
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case AMDGPU::SI_KILL:
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if (Depth == 0)
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SkipIfDead(MI);
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else
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if (Depth == 0) {
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if (skipIfDead(MI)) {
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NextBB = std::next(BI);
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BE = MF.end();
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Next = MBB.end();
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}
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} else
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HaveKill = true;
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Kill(MI);
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break;
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@ -3,7 +3,7 @@
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# CHECK-LABEL: name: extract_undef_offset_vgpr{{$}}
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# CHECK: bb.1:
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# CHECK: successors: %bb.1(0x40000000 / 0x80000000 = 50.00%), %bb.2(0x40000000 / 0x80000000 = 50.00%)
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# CHECK: successors: %bb.2(0x40000000 / 0x80000000 = 50.00%), %bb.1(0x40000000 / 0x80000000 = 50.00%)
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# CHECK: liveins: %vgpr0_vgpr1_vgpr2_vgpr3{{$}}
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# CHECK: V_READFIRSTLANE_B32 undef %vgpr10, implicit %exec
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@ -103,7 +103,7 @@ body: |
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# CHECK-LABEL: name: extract_undef_neg_offset_vgpr{{$}}
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# CHECK: bb.1:
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# CHECK: successors: %bb.1(0x40000000 / 0x80000000 = 50.00%), %bb.2(0x40000000 / 0x80000000 = 50.00%)
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# CHECK: successors: %bb.2(0x40000000 / 0x80000000 = 50.00%), %bb.1(0x40000000 / 0x80000000 = 50.00%)
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# CHECK: liveins: %vgpr0_vgpr1_vgpr2_vgpr3{{$}}
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# CHECK: %vcc_lo = V_READFIRSTLANE_B32 undef %vgpr10, implicit %exec
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@ -159,7 +159,7 @@ body: |
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# CHECK-LABEL: name: insert_undef_offset_vgpr{{$}}
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# CHECK: bb.1:
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# CHECK: successors: %bb.1(0x40000000 / 0x80000000 = 50.00%), %bb.2(0x40000000 / 0x80000000 = 50.00%)
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# CHECK: successors: %bb.2(0x40000000 / 0x80000000 = 50.00%), %bb.1(0x40000000 / 0x80000000 = 50.00%)
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# CHECK: liveins: %vgpr4, %vgpr0_vgpr1_vgpr2_vgpr3{{$}}
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# CHECK: %vcc_lo = V_READFIRSTLANE_B32 undef %vgpr10, implicit %exec
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@ -215,7 +215,7 @@ body: |
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# CHECK-LABEL: name: insert_undef_neg_offset_vgpr{{$}}
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# CHECK: bb.1:
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# CHECK: successors: %bb.1(0x40000000 / 0x80000000 = 50.00%), %bb.2(0x40000000 / 0x80000000 = 50.00%)
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# CHECK: successors: %bb.2(0x40000000 / 0x80000000 = 50.00%), %bb.1(0x40000000 / 0x80000000 = 50.00%)
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# CHECK: liveins: %vgpr4, %vgpr0_vgpr1_vgpr2_vgpr3{{$}}
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# CHECK: %vcc_lo = V_READFIRSTLANE_B32 undef %vgpr10, implicit %exec
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@ -272,7 +272,7 @@ body: |
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# CHECK-LABEL: insert_undef_value_offset_vgpr{{$}}
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# CHECK: bb.1:
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# CHECK: successors: %bb.1(0x40000000 / 0x80000000 = 50.00%), %bb.2(0x40000000 / 0x80000000 = 50.00%)
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# CHECK: successors: %bb.2(0x40000000 / 0x80000000 = 50.00%), %bb.1(0x40000000 / 0x80000000 = 50.00%)
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# CHECK: liveins: %vgpr4, %vgpr0_vgpr1_vgpr2_vgpr3{{$}}
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# CHECK: %vcc_lo = V_READFIRSTLANE_B32 %vgpr4, implicit %exec
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@ -0,0 +1,145 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
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; CHECK-LABEL: {{^}}test_kill_depth_0_imm_pos:
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; CHECK-NEXT: ; BB#0:
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @test_kill_depth_0_imm_pos() #0 {
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call void @llvm.AMDGPU.kill(float 0.0)
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ret void
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}
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; CHECK-LABEL: {{^}}test_kill_depth_0_imm_neg:
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; CHECK-NEXT: ; BB#0:
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; CHECK-NEXT: s_mov_b64 exec, 0
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @test_kill_depth_0_imm_neg() #0 {
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call void @llvm.AMDGPU.kill(float -0.0)
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ret void
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}
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; CHECK-LABEL: {{^}}test_kill_depth_var:
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; CHECK-NEXT: ; BB#0:
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; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v0
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @test_kill_depth_var(float %x) #0 {
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call void @llvm.AMDGPU.kill(float %x)
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ret void
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}
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; FIXME: why does the skip depend on the asm length in the same block?
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; CHECK-LABEL: {{^}}test_kill_control_flow:
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; CHECK: s_cmp_lg_i32 s{{[0-9]+}}, 0
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; CHECK: s_cbranch_scc1 [[RETURN_BB:BB[0-9]+_[0-9]+]]
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; CHECK: ; BB#1:
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: v_nop_e64
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; CHECK: s_cbranch_execnz [[SPLIT_BB:BB[0-9]+_[0-9]+]]
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; CHECK-NEXT: ; BB#3:
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; CHECK-NEXT: exp 0, 9, 0, 1, 1, v0, v0, v0, v0
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; CHECK-NEXT: s_endpgm
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; CHECK-NEXT: {{^}}[[SPLIT_BB]]:
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; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v7
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; CHECK-NEXT: {{^}}BB{{[0-9]+_[0-9]+}}:
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; CHECK-NEXT: s_endpgm
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define amdgpu_ps void @test_kill_control_flow(i32 inreg %arg) #0 {
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entry:
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%cmp = icmp eq i32 %arg, 0
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br i1 %cmp, label %bb, label %exit
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bb:
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%var = call float asm sideeffect "
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v_mov_b32_e64 v7, -1
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64", "={VGPR7}"()
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call void @llvm.AMDGPU.kill(float %var)
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br label %exit
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exit:
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ret void
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}
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; CHECK-LABEL: {{^}}test_kill_control_flow_remainder:
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; CHECK: s_cmp_lg_i32 s{{[0-9]+}}, 0
|
||||
; CHECK-NEXT: s_cbranch_scc1 [[RETURN_BB:BB[0-9]+_[0-9]+]]
|
||||
|
||||
; CHECK-NEXT: ; BB#1: ; %bb
|
||||
; CHECK: v_mov_b32_e64 v7, -1
|
||||
; CHECK: v_nop_e64
|
||||
; CHECK: v_nop_e64
|
||||
; CHECK: v_nop_e64
|
||||
; CHECK: v_nop_e64
|
||||
; CHECK: v_nop_e64
|
||||
; CHECK: v_nop_e64
|
||||
; CHECK: v_nop_e64
|
||||
; CHECK: v_nop_e64
|
||||
; CHECK: ;;#ASMEND
|
||||
; CHECK: v_mov_b32_e64 v8, -1
|
||||
; CHECK: ;;#ASMEND
|
||||
; CHECK-NEXT: s_cbranch_execnz [[SPLIT_BB:BB[0-9]+_[0-9]+]]
|
||||
|
||||
; CHECK-NEXT: ; BB#3:
|
||||
; CHECK-NEXT: exp 0, 9, 0, 1, 1, v0, v0, v0, v0
|
||||
; CHECK-NEXT: s_endpgm
|
||||
|
||||
; CHECK-NEXT: {{^}}[[SPLIT_BB]]:
|
||||
; CHECK-NEXT: v_cmpx_le_f32_e32 vcc, 0, v7
|
||||
; CHECK: buffer_store_dword v8
|
||||
; CHECK: v_mov_b32_e64 v9, -2
|
||||
|
||||
; CHECK: {{^}}BB{{[0-9]+_[0-9]+}}:
|
||||
; CHECK: buffer_store_dword v9
|
||||
; CHECK-NEXT: s_endpgm
|
||||
define amdgpu_ps void @test_kill_control_flow_remainder(i32 inreg %arg) #0 {
|
||||
entry:
|
||||
%cmp = icmp eq i32 %arg, 0
|
||||
br i1 %cmp, label %bb, label %exit
|
||||
|
||||
bb:
|
||||
%var = call float asm sideeffect "
|
||||
v_mov_b32_e64 v7, -1
|
||||
v_nop_e64
|
||||
v_nop_e64
|
||||
v_nop_e64
|
||||
v_nop_e64
|
||||
v_nop_e64
|
||||
v_nop_e64
|
||||
v_nop_e64
|
||||
v_nop_e64
|
||||
v_nop_e64
|
||||
v_nop_e64
|
||||
v_nop_e64", "={VGPR7}"()
|
||||
%live.across = call float asm sideeffect "v_mov_b32_e64 v8, -1", "={VGPR8}"()
|
||||
call void @llvm.AMDGPU.kill(float %var)
|
||||
store volatile float %live.across, float addrspace(1)* undef
|
||||
%live.out = call float asm sideeffect "v_mov_b32_e64 v9, -2", "={VGPR9}"()
|
||||
br label %exit
|
||||
|
||||
exit:
|
||||
%phi = phi float [ 0.0, %entry ], [ %live.out, %bb ]
|
||||
store float %phi, float addrspace(1)* undef
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.AMDGPU.kill(float) #0
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
Loading…
Reference in New Issue