forked from OSchip/llvm-project
[lldb] [Process/Utility] Define qN regs on ARM via helper macro
Add a FPU_QREG macro to define qN registers. This is a piece-wise attempt of reconstructing D112066 with the goal of figuring out which part of the larger change breaks the buildbot. Differential Revision: https://reviews.llvm.org/D112066
This commit is contained in:
Michał Górny
parent
9fc523d114
commit
6561c074c0
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@ -320,6 +320,15 @@ static uint32_t g_q15_contains[] = {fpu_d30, fpu_d31, LLDB_INVALID_REGNUM};
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nullptr, g_##name##_invalidates, \
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}
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#define FPU_QREG(name, offset) \
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{ \
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#name, nullptr, 16, FPU_OFFSET(offset), eEncodingVector, \
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eFormatVectorOfUInt8, \
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{LLDB_INVALID_REGNUM, dwarf_##name, LLDB_INVALID_REGNUM, \
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LLDB_INVALID_REGNUM, fpu_##name }, \
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g_##name##_contains, nullptr, \
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}
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static RegisterInfo g_register_infos_arm[] = {
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// NAME ALT SZ OFFSET ENCODING FORMAT
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// EH_FRAME DWARF GENERIC
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@ -612,198 +621,22 @@ static RegisterInfo g_register_infos_arm[] = {
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FPU_REG(d30, 8, 60, q15),
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FPU_REG(d31, 8, 62, q15),
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{
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"q0",
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nullptr,
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16,
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FPU_OFFSET(0),
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eEncodingVector,
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eFormatVectorOfUInt8,
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{LLDB_INVALID_REGNUM, dwarf_q0, LLDB_INVALID_REGNUM,
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LLDB_INVALID_REGNUM, fpu_q0},
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g_q0_contains,
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nullptr,
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},
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{
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"q1",
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nullptr,
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16,
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FPU_OFFSET(4),
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eEncodingVector,
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eFormatVectorOfUInt8,
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{LLDB_INVALID_REGNUM, dwarf_q1, LLDB_INVALID_REGNUM,
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LLDB_INVALID_REGNUM, fpu_q1},
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g_q1_contains,
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nullptr,
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},
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{
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"q2",
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nullptr,
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16,
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FPU_OFFSET(8),
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eEncodingVector,
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eFormatVectorOfUInt8,
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{LLDB_INVALID_REGNUM, dwarf_q2, LLDB_INVALID_REGNUM,
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LLDB_INVALID_REGNUM, fpu_q2},
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g_q2_contains,
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nullptr,
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},
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{
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"q3",
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nullptr,
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16,
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FPU_OFFSET(12),
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eEncodingVector,
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eFormatVectorOfUInt8,
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{LLDB_INVALID_REGNUM, dwarf_q3, LLDB_INVALID_REGNUM,
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LLDB_INVALID_REGNUM, fpu_q3},
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g_q3_contains,
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nullptr,
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},
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{
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"q4",
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nullptr,
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16,
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FPU_OFFSET(16),
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eEncodingVector,
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eFormatVectorOfUInt8,
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{LLDB_INVALID_REGNUM, dwarf_q4, LLDB_INVALID_REGNUM,
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LLDB_INVALID_REGNUM, fpu_q4},
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g_q4_contains,
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nullptr,
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},
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{
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"q5",
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nullptr,
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16,
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FPU_OFFSET(20),
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eEncodingVector,
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eFormatVectorOfUInt8,
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{LLDB_INVALID_REGNUM, dwarf_q5, LLDB_INVALID_REGNUM,
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LLDB_INVALID_REGNUM, fpu_q5},
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g_q5_contains,
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nullptr,
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},
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{
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"q6",
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nullptr,
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16,
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FPU_OFFSET(24),
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eEncodingVector,
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eFormatVectorOfUInt8,
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{LLDB_INVALID_REGNUM, dwarf_q6, LLDB_INVALID_REGNUM,
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LLDB_INVALID_REGNUM, fpu_q6},
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g_q6_contains,
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nullptr,
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},
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{
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"q7",
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nullptr,
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16,
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FPU_OFFSET(28),
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eEncodingVector,
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eFormatVectorOfUInt8,
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{LLDB_INVALID_REGNUM, dwarf_q7, LLDB_INVALID_REGNUM,
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LLDB_INVALID_REGNUM, fpu_q7},
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g_q7_contains,
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nullptr,
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},
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{
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"q8",
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nullptr,
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16,
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FPU_OFFSET(32),
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eEncodingVector,
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eFormatVectorOfUInt8,
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{LLDB_INVALID_REGNUM, dwarf_q8, LLDB_INVALID_REGNUM,
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LLDB_INVALID_REGNUM, fpu_q8},
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g_q8_contains,
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nullptr,
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},
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{
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"q9",
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nullptr,
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16,
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FPU_OFFSET(36),
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eEncodingVector,
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eFormatVectorOfUInt8,
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{LLDB_INVALID_REGNUM, dwarf_q9, LLDB_INVALID_REGNUM,
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LLDB_INVALID_REGNUM, fpu_q9},
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g_q9_contains,
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nullptr,
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},
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{
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"q10",
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nullptr,
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16,
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FPU_OFFSET(40),
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eEncodingVector,
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eFormatVectorOfUInt8,
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{LLDB_INVALID_REGNUM, dwarf_q10, LLDB_INVALID_REGNUM,
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LLDB_INVALID_REGNUM, fpu_q10},
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g_q10_contains,
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nullptr,
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},
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{
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"q11",
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nullptr,
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16,
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FPU_OFFSET(44),
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eEncodingVector,
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eFormatVectorOfUInt8,
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{LLDB_INVALID_REGNUM, dwarf_q11, LLDB_INVALID_REGNUM,
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LLDB_INVALID_REGNUM, fpu_q11},
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g_q11_contains,
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nullptr,
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},
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{
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"q12",
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nullptr,
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16,
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FPU_OFFSET(48),
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eEncodingVector,
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eFormatVectorOfUInt8,
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{LLDB_INVALID_REGNUM, dwarf_q12, LLDB_INVALID_REGNUM,
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LLDB_INVALID_REGNUM, fpu_q12},
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g_q12_contains,
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nullptr,
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},
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{
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"q13",
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nullptr,
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16,
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FPU_OFFSET(52),
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eEncodingVector,
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eFormatVectorOfUInt8,
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{LLDB_INVALID_REGNUM, dwarf_q13, LLDB_INVALID_REGNUM,
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LLDB_INVALID_REGNUM, fpu_q13},
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g_q13_contains,
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nullptr,
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},
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{
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"q14",
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nullptr,
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16,
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FPU_OFFSET(56),
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eEncodingVector,
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eFormatVectorOfUInt8,
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{LLDB_INVALID_REGNUM, dwarf_q14, LLDB_INVALID_REGNUM,
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LLDB_INVALID_REGNUM, fpu_q14},
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g_q14_contains,
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nullptr,
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},
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{
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"q15",
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nullptr,
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16,
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FPU_OFFSET(60),
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eEncodingVector,
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eFormatVectorOfUInt8,
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{LLDB_INVALID_REGNUM, dwarf_q15, LLDB_INVALID_REGNUM,
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LLDB_INVALID_REGNUM, fpu_q15},
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g_q15_contains,
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nullptr,
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},
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FPU_QREG(q0, 0),
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FPU_QREG(q1, 4),
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FPU_QREG(q2, 8),
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FPU_QREG(q3, 12),
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FPU_QREG(q4, 16),
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FPU_QREG(q5, 20),
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FPU_QREG(q6, 24),
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FPU_QREG(q7, 28),
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FPU_QREG(q8, 32),
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FPU_QREG(q9, 36),
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FPU_QREG(q10, 40),
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FPU_QREG(q11, 44),
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FPU_QREG(q12, 48),
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FPU_QREG(q13, 52),
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FPU_QREG(q14, 56),
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FPU_QREG(q15, 60),
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{
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"exception",
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