forked from OSchip/llvm-project
[Hexagon] Rename operand/predicate names for unshifted integers
For example, rename s6Ext to s6_0Ext. The names for shifted integers include the underscore and this will make the naming consistent. It also exposed a few duplicates that were removed. llvm-svn: 285728
This commit is contained in:
Krzysztof Parzyszek
parent
63db2395f6
commit
654dc11b79
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@ -276,55 +276,52 @@ public:
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}
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bool isf32Ext() const { return false; }
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bool iss32Imm() const { return CheckImmRange(32, 0, true, true, false); }
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bool iss32_0Imm() const { return CheckImmRange(32, 0, true, true, false); }
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bool iss23_2Imm() const { return CheckImmRange(23, 2, true, true, false); }
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bool iss8Imm() const { return CheckImmRange(8, 0, true, false, false); }
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bool iss8Imm64() const { return CheckImmRange(8, 0, true, true, false); }
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bool iss7Imm() const { return CheckImmRange(7, 0, true, false, false); }
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bool iss6Imm() const { return CheckImmRange(6, 0, true, false, false); }
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bool iss4Imm() const { return CheckImmRange(4, 0, true, false, false); }
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bool iss8_0Imm() const { return CheckImmRange(8, 0, true, false, false); }
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bool iss8_0Imm64() const { return CheckImmRange(8, 0, true, true, false); }
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bool iss7_0Imm() const { return CheckImmRange(7, 0, true, false, false); }
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bool iss6_0Imm() const { return CheckImmRange(6, 0, true, false, false); }
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bool iss4_0Imm() const { return CheckImmRange(4, 0, true, false, false); }
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bool iss4_1Imm() const { return CheckImmRange(4, 1, true, false, false); }
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bool iss4_2Imm() const { return CheckImmRange(4, 2, true, false, false); }
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bool iss4_3Imm() const { return CheckImmRange(4, 3, true, false, false); }
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bool iss4_6Imm() const { return CheckImmRange(4, 0, true, false, false); }
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bool iss3_6Imm() const { return CheckImmRange(3, 0, true, false, false); }
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bool iss3Imm() const { return CheckImmRange(3, 0, true, false, false); }
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bool iss3_0Imm() const { return CheckImmRange(3, 0, true, false, false); }
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bool isu64Imm() const { return CheckImmRange(64, 0, false, true, true); }
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bool isu32Imm() const { return CheckImmRange(32, 0, false, true, false); }
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bool isu64_0Imm() const { return CheckImmRange(64, 0, false, true, true); }
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bool isu32_0Imm() const { return CheckImmRange(32, 0, false, true, false); }
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bool isu26_6Imm() const { return CheckImmRange(26, 6, false, true, false); }
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bool isu16Imm() const { return CheckImmRange(16, 0, false, true, false); }
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bool isu16_0Imm() const { return CheckImmRange(16, 0, false, true, false); }
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bool isu16_1Imm() const { return CheckImmRange(16, 1, false, true, false); }
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bool isu16_2Imm() const { return CheckImmRange(16, 2, false, true, false); }
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bool isu16_3Imm() const { return CheckImmRange(16, 3, false, true, false); }
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bool isu11_3Imm() const { return CheckImmRange(11, 3, false, false, false); }
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bool isu6_0Imm() const { return CheckImmRange(6, 0, false, false, false); }
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bool isu6_1Imm() const { return CheckImmRange(6, 1, false, false, false); }
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bool isu6_2Imm() const { return CheckImmRange(6, 2, false, false, false); }
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bool isu6_3Imm() const { return CheckImmRange(6, 3, false, false, false); }
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bool isu10Imm() const { return CheckImmRange(10, 0, false, false, false); }
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bool isu9Imm() const { return CheckImmRange(9, 0, false, false, false); }
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bool isu8Imm() const { return CheckImmRange(8, 0, false, false, false); }
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bool isu7Imm() const { return CheckImmRange(7, 0, false, false, false); }
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bool isu6Imm() const { return CheckImmRange(6, 0, false, false, false); }
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bool isu5Imm() const { return CheckImmRange(5, 0, false, false, false); }
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bool isu4Imm() const { return CheckImmRange(4, 0, false, false, false); }
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bool isu3Imm() const { return CheckImmRange(3, 0, false, false, false); }
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bool isu2Imm() const { return CheckImmRange(2, 0, false, false, false); }
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bool isu1Imm() const { return CheckImmRange(1, 0, false, false, false); }
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bool isu10_0Imm() const { return CheckImmRange(10, 0, false, false, false); }
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bool isu9_0Imm() const { return CheckImmRange(9, 0, false, false, false); }
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bool isu8_0Imm() const { return CheckImmRange(8, 0, false, false, false); }
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bool isu7_0Imm() const { return CheckImmRange(7, 0, false, false, false); }
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bool isu6_0Imm() const { return CheckImmRange(6, 0, false, false, false); }
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bool isu5_0Imm() const { return CheckImmRange(5, 0, false, false, false); }
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bool isu4_0Imm() const { return CheckImmRange(4, 0, false, false, false); }
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bool isu3_0Imm() const { return CheckImmRange(3, 0, false, false, false); }
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bool isu2_0Imm() const { return CheckImmRange(2, 0, false, false, false); }
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bool isu1_0Imm() const { return CheckImmRange(1, 0, false, false, false); }
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bool ism6Imm() const { return CheckImmRange(6, 0, false, false, false); }
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bool isn8Imm() const { return CheckImmRange(8, 0, false, false, false); }
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bool ism6_0Imm() const { return CheckImmRange(6, 0, false, false, false); }
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bool isn8_0Imm() const { return CheckImmRange(8, 0, false, false, false); }
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bool iss16Ext() const { return CheckImmRange(16 + 26, 0, true, true, true); }
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bool iss12Ext() const { return CheckImmRange(12 + 26, 0, true, true, true); }
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bool iss10Ext() const { return CheckImmRange(10 + 26, 0, true, true, true); }
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bool iss9Ext() const { return CheckImmRange(9 + 26, 0, true, true, true); }
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bool iss8Ext() const { return CheckImmRange(8 + 26, 0, true, true, true); }
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bool iss7Ext() const { return CheckImmRange(7 + 26, 0, true, true, true); }
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bool iss6Ext() const { return CheckImmRange(6 + 26, 0, true, true, true); }
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bool iss16_0Ext() const { return CheckImmRange(16 + 26, 0, true, true, true); }
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bool iss12_0Ext() const { return CheckImmRange(12 + 26, 0, true, true, true); }
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bool iss10_0Ext() const { return CheckImmRange(10 + 26, 0, true, true, true); }
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bool iss9_0Ext() const { return CheckImmRange(9 + 26, 0, true, true, true); }
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bool iss8_0Ext() const { return CheckImmRange(8 + 26, 0, true, true, true); }
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bool iss7_0Ext() const { return CheckImmRange(7 + 26, 0, true, true, true); }
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bool iss6_0Ext() const { return CheckImmRange(6 + 26, 0, true, true, true); }
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bool iss11_0Ext() const {
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return CheckImmRange(11 + 26, 0, true, true, true);
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}
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@ -338,16 +335,15 @@ public:
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return CheckImmRange(11 + 26, 3, true, true, true);
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}
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bool isu6Ext() const { return CheckImmRange(6 + 26, 0, false, true, true); }
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bool isu7Ext() const { return CheckImmRange(7 + 26, 0, false, true, true); }
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bool isu8Ext() const { return CheckImmRange(8 + 26, 0, false, true, true); }
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bool isu9Ext() const { return CheckImmRange(9 + 26, 0, false, true, true); }
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bool isu10Ext() const { return CheckImmRange(10 + 26, 0, false, true, true); }
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bool isu7_0Ext() const { return CheckImmRange(7 + 26, 0, false, true, true); }
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bool isu8_0Ext() const { return CheckImmRange(8 + 26, 0, false, true, true); }
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bool isu9_0Ext() const { return CheckImmRange(9 + 26, 0, false, true, true); }
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bool isu10_0Ext() const { return CheckImmRange(10 + 26, 0, false, true, true); }
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bool isu6_0Ext() const { return CheckImmRange(6 + 26, 0, false, true, true); }
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bool isu6_1Ext() const { return CheckImmRange(6 + 26, 1, false, true, true); }
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bool isu6_2Ext() const { return CheckImmRange(6 + 26, 2, false, true, true); }
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bool isu6_3Ext() const { return CheckImmRange(6 + 26, 3, false, true, true); }
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bool isu32MustExt() const { return isImm(); }
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bool isu32_0MustExt() const { return isImm(); }
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void addRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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@ -378,22 +374,19 @@ public:
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addImmOperands(Inst, N);
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}
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void adds32ImmOperands(MCInst &Inst, unsigned N) const {
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void adds32_0ImmOperands(MCInst &Inst, unsigned N) const {
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addSignedImmOperands(Inst, N);
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}
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void adds23_2ImmOperands(MCInst &Inst, unsigned N) const {
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addSignedImmOperands(Inst, N);
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}
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void adds8ImmOperands(MCInst &Inst, unsigned N) const {
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void adds8_0ImmOperands(MCInst &Inst, unsigned N) const {
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addSignedImmOperands(Inst, N);
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}
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void adds8Imm64Operands(MCInst &Inst, unsigned N) const {
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void adds8_0Imm64Operands(MCInst &Inst, unsigned N) const {
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addSignedImmOperands(Inst, N);
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}
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void adds6ImmOperands(MCInst &Inst, unsigned N) const {
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addSignedImmOperands(Inst, N);
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}
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void adds4ImmOperands(MCInst &Inst, unsigned N) const {
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void adds6_0ImmOperands(MCInst &Inst, unsigned N) const {
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addSignedImmOperands(Inst, N);
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}
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void adds4_0ImmOperands(MCInst &Inst, unsigned N) const {
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@ -408,22 +401,19 @@ public:
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void adds4_3ImmOperands(MCInst &Inst, unsigned N) const {
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addSignedImmOperands(Inst, N);
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}
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void adds3ImmOperands(MCInst &Inst, unsigned N) const {
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void adds3_0ImmOperands(MCInst &Inst, unsigned N) const {
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addSignedImmOperands(Inst, N);
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}
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void addu64ImmOperands(MCInst &Inst, unsigned N) const {
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void addu64_0ImmOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addu32ImmOperands(MCInst &Inst, unsigned N) const {
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void addu32_0ImmOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addu26_6ImmOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addu16ImmOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addu16_0ImmOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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@ -439,19 +429,16 @@ public:
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void addu11_3ImmOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addu10ImmOperands(MCInst &Inst, unsigned N) const {
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void addu10_0ImmOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addu9ImmOperands(MCInst &Inst, unsigned N) const {
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void addu9_0ImmOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addu8ImmOperands(MCInst &Inst, unsigned N) const {
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void addu8_0ImmOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addu7ImmOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addu6ImmOperands(MCInst &Inst, unsigned N) const {
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void addu7_0ImmOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addu6_0ImmOperands(MCInst &Inst, unsigned N) const {
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@ -466,45 +453,45 @@ public:
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void addu6_3ImmOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addu5ImmOperands(MCInst &Inst, unsigned N) const {
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void addu5_0ImmOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addu4ImmOperands(MCInst &Inst, unsigned N) const {
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void addu4_0ImmOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addu3ImmOperands(MCInst &Inst, unsigned N) const {
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void addu3_0ImmOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addu2ImmOperands(MCInst &Inst, unsigned N) const {
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void addu2_0ImmOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addu1ImmOperands(MCInst &Inst, unsigned N) const {
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void addu1_0ImmOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addm6ImmOperands(MCInst &Inst, unsigned N) const {
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void addm6_0ImmOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addn8ImmOperands(MCInst &Inst, unsigned N) const {
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void addn8_0ImmOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void adds16ExtOperands(MCInst &Inst, unsigned N) const {
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void adds16_0ExtOperands(MCInst &Inst, unsigned N) const {
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addSignedImmOperands(Inst, N);
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}
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void adds12ExtOperands(MCInst &Inst, unsigned N) const {
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void adds12_0ExtOperands(MCInst &Inst, unsigned N) const {
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addSignedImmOperands(Inst, N);
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}
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void adds10ExtOperands(MCInst &Inst, unsigned N) const {
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void adds10_0ExtOperands(MCInst &Inst, unsigned N) const {
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addSignedImmOperands(Inst, N);
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}
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void adds9ExtOperands(MCInst &Inst, unsigned N) const {
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void adds9_0ExtOperands(MCInst &Inst, unsigned N) const {
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addSignedImmOperands(Inst, N);
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}
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void adds8ExtOperands(MCInst &Inst, unsigned N) const {
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void adds8_0ExtOperands(MCInst &Inst, unsigned N) const {
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addSignedImmOperands(Inst, N);
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}
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void adds6ExtOperands(MCInst &Inst, unsigned N) const {
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void adds6_0ExtOperands(MCInst &Inst, unsigned N) const {
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addSignedImmOperands(Inst, N);
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}
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void adds11_0ExtOperands(MCInst &Inst, unsigned N) const {
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@ -520,19 +507,16 @@ public:
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addSignedImmOperands(Inst, N);
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}
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void addu6ExtOperands(MCInst &Inst, unsigned N) const {
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void addu7_0ExtOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addu7ExtOperands(MCInst &Inst, unsigned N) const {
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void addu8_0ExtOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addu8ExtOperands(MCInst &Inst, unsigned N) const {
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void addu9_0ExtOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addu9ExtOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addu10ExtOperands(MCInst &Inst, unsigned N) const {
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void addu10_0ExtOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addu6_0ExtOperands(MCInst &Inst, unsigned N) const {
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@ -547,7 +531,7 @@ public:
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void addu6_3ExtOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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void addu32MustExtOperands(MCInst &Inst, unsigned N) const {
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void addu32_0MustExtOperands(MCInst &Inst, unsigned N) const {
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addImmOperands(Inst, N);
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}
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@ -105,9 +105,9 @@ static unsigned getRegFromSubinstEncoding(unsigned encoded_reg);
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static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t Address, const void *Decoder);
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static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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static DecodeStatus s16_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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static DecodeStatus s12_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s11_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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@ -117,9 +117,9 @@ static DecodeStatus s11_2ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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static DecodeStatus s10_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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static DecodeStatus s6_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t Address,
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const void *Decoder);
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@ -663,13 +663,13 @@ static DecodeStatus unsignedImmDecoder(MCInst &MI, unsigned tmp,
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return MCDisassembler::Success;
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}
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static DecodeStatus s16ImmDecoder(MCInst &MI, unsigned tmp,
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static DecodeStatus s16_0ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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signedDecoder<16>(MI, tmp, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus s12ImmDecoder(MCInst &MI, unsigned tmp,
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static DecodeStatus s12_0ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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signedDecoder<12>(MI, tmp, Decoder);
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return MCDisassembler::Success;
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@ -699,13 +699,13 @@ static DecodeStatus s11_3ImmDecoder(MCInst &MI, unsigned tmp,
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return MCDisassembler::Success;
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}
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static DecodeStatus s10ImmDecoder(MCInst &MI, unsigned tmp,
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static DecodeStatus s10_0ImmDecoder(MCInst &MI, unsigned tmp,
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uint64_t /*Address*/, const void *Decoder) {
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signedDecoder<10>(MI, tmp, Decoder);
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return MCDisassembler::Success;
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}
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static DecodeStatus s8ImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/,
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static DecodeStatus s8_0ImmDecoder(MCInst &MI, unsigned tmp, uint64_t /*Address*/,
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const void *Decoder) {
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signedDecoder<8>(MI, tmp, Decoder);
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return MCDisassembler::Success;
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@ -63,34 +63,34 @@ def : InstAlias<"memw($Rs) = $Rt.new",
|
|||
(S2_storerinew_io IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
|
||||
|
||||
def : InstAlias<"memb($Rs) = #$S8",
|
||||
(S4_storeirb_io IntRegs:$Rs, 0, s8Ext:$S8), 0>;
|
||||
(S4_storeirb_io IntRegs:$Rs, 0, s8_0Ext:$S8), 0>;
|
||||
|
||||
def : InstAlias<"memh($Rs) = #$S8",
|
||||
(S4_storeirh_io IntRegs:$Rs, 0, s8Ext:$S8), 0>;
|
||||
(S4_storeirh_io IntRegs:$Rs, 0, s8_0Ext:$S8), 0>;
|
||||
|
||||
def : InstAlias<"memw($Rs) = #$S8",
|
||||
(S4_storeiri_io IntRegs:$Rs, 0, s8Ext:$S8), 0>;
|
||||
(S4_storeiri_io IntRegs:$Rs, 0, s8_0Ext:$S8), 0>;
|
||||
|
||||
def : InstAlias<"memd($Rs) = $Rtt",
|
||||
(S2_storerd_io IntRegs:$Rs, 0, DoubleRegs:$Rtt), 0>;
|
||||
|
||||
def : InstAlias<"memb($Rs) = setbit(#$U5)",
|
||||
(L4_ior_memopb_io IntRegs:$Rs, 0, u5Imm:$U5), 0>;
|
||||
(L4_ior_memopb_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>;
|
||||
|
||||
def : InstAlias<"memh($Rs) = setbit(#$U5)",
|
||||
(L4_ior_memoph_io IntRegs:$Rs, 0, u5Imm:$U5), 0>;
|
||||
(L4_ior_memoph_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>;
|
||||
|
||||
def : InstAlias<"memw($Rs) = setbit(#$U5)",
|
||||
(L4_ior_memopw_io IntRegs:$Rs, 0, u5Imm:$U5), 0>;
|
||||
(L4_ior_memopw_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>;
|
||||
|
||||
def : InstAlias<"memb($Rs) = clrbit(#$U5)",
|
||||
(L4_iand_memopb_io IntRegs:$Rs, 0, u5Imm:$U5), 0>;
|
||||
(L4_iand_memopb_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>;
|
||||
|
||||
def : InstAlias<"memh($Rs) = clrbit(#$U5)",
|
||||
(L4_iand_memoph_io IntRegs:$Rs, 0, u5Imm:$U5), 0>;
|
||||
(L4_iand_memoph_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>;
|
||||
|
||||
def : InstAlias<"memw($Rs) = clrbit(#$U5)",
|
||||
(L4_iand_memopw_io IntRegs:$Rs, 0, u5Imm:$U5), 0>;
|
||||
(L4_iand_memopw_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>;
|
||||
|
||||
// Alias of: $Rd = memXX($Rs+#XX) to $Rd = memXX($Rs)
|
||||
def : InstAlias<"$Rd = memb($Rs)",
|
||||
|
|
@ -241,40 +241,40 @@ def : InstAlias<"if (!$Pt.new) memw($Rs) = $Rt.new",
|
|||
(S4_pstorerinewfnew_io PredRegs:$Pt, IntRegs:$Rs, 0, IntRegs:$Rt), 0>;
|
||||
|
||||
def : InstAlias<"if ($Pt) memb($Rs) = #$S6",
|
||||
(S4_storeirbt_io PredRegs:$Pt, IntRegs:$Rs, 0, s6Ext:$S6), 0>;
|
||||
(S4_storeirbt_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>;
|
||||
|
||||
def : InstAlias<"if ($Pt) memh($Rs) = #$S6",
|
||||
(S4_storeirht_io PredRegs:$Pt, IntRegs:$Rs, 0, s6Ext:$S6), 0>;
|
||||
(S4_storeirht_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>;
|
||||
|
||||
def : InstAlias<"if ($Pt) memw($Rs) = #$S6",
|
||||
(S4_storeirit_io PredRegs:$Pt, IntRegs:$Rs, 0, s6Ext:$S6), 0>;
|
||||
(S4_storeirit_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>;
|
||||
|
||||
def : InstAlias<"if ($Pt.new) memb($Rs) = #$S6",
|
||||
(S4_storeirbtnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6Ext:$S6), 0>;
|
||||
(S4_storeirbtnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>;
|
||||
|
||||
def : InstAlias<"if ($Pt.new) memh($Rs) = #$S6",
|
||||
(S4_storeirhtnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6Ext:$S6), 0>;
|
||||
(S4_storeirhtnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>;
|
||||
|
||||
def : InstAlias<"if ($Pt.new) memw($Rs) = #$S6",
|
||||
(S4_storeiritnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6Ext:$S6), 0>;
|
||||
(S4_storeiritnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>;
|
||||
|
||||
def : InstAlias<"if (!$Pt) memb($Rs) = #$S6",
|
||||
(S4_storeirbf_io PredRegs:$Pt, IntRegs:$Rs, 0, s6Ext:$S6), 0>;
|
||||
(S4_storeirbf_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>;
|
||||
|
||||
def : InstAlias<"if (!$Pt) memh($Rs) = #$S6",
|
||||
(S4_storeirhf_io PredRegs:$Pt, IntRegs:$Rs, 0, s6Ext:$S6), 0>;
|
||||
(S4_storeirhf_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>;
|
||||
|
||||
def : InstAlias<"if (!$Pt) memw($Rs) = #$S6",
|
||||
(S4_storeirif_io PredRegs:$Pt, IntRegs:$Rs, 0, s6Ext:$S6), 0>;
|
||||
(S4_storeirif_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>;
|
||||
|
||||
def : InstAlias<"if (!$Pt.new) memb($Rs) = #$S6",
|
||||
(S4_storeirbfnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6Ext:$S6), 0>;
|
||||
(S4_storeirbfnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>;
|
||||
|
||||
def : InstAlias<"if (!$Pt.new) memh($Rs) = #$S6",
|
||||
(S4_storeirhfnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6Ext:$S6), 0>;
|
||||
(S4_storeirhfnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>;
|
||||
|
||||
def : InstAlias<"if (!$Pt.new) memw($Rs) = #$S6",
|
||||
(S4_storeirifnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6Ext:$S6), 0>;
|
||||
(S4_storeirifnew_io PredRegs:$Pt, IntRegs:$Rs, 0, s6_0Ext:$S6), 0>;
|
||||
|
||||
// Alias of: memXX($Rs + $u6_X) |= $Rt, also &=, +=, -=
|
||||
// to: memXX($Rs) |= $Rt
|
||||
|
|
@ -295,11 +295,11 @@ def : InstAlias<"memb($Rs) -= $Rt",
|
|||
Requires<[UseMEMOP]>;
|
||||
|
||||
def : InstAlias<"memb($Rs) += #$U5",
|
||||
(L4_iadd_memopb_io IntRegs:$Rs, 0, u5Imm:$U5), 0>,
|
||||
(L4_iadd_memopb_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>,
|
||||
Requires<[UseMEMOP]>;
|
||||
|
||||
def : InstAlias<"memb($Rs) -= #$U5",
|
||||
(L4_isub_memopb_io IntRegs:$Rs, 0, u5Imm:$U5), 0>,
|
||||
(L4_isub_memopb_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>,
|
||||
Requires<[UseMEMOP]>;
|
||||
|
||||
def : InstAlias<"memh($Rs) &= $Rt",
|
||||
|
|
@ -319,11 +319,11 @@ def : InstAlias<"memh($Rs) -= $Rt",
|
|||
Requires<[UseMEMOP]>;
|
||||
|
||||
def : InstAlias<"memh($Rs) += #$U5",
|
||||
(L4_iadd_memoph_io IntRegs:$Rs, 0, u5Imm:$U5), 0>,
|
||||
(L4_iadd_memoph_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>,
|
||||
Requires<[UseMEMOP]>;
|
||||
|
||||
def : InstAlias<"memh($Rs) -= #$U5",
|
||||
(L4_isub_memoph_io IntRegs:$Rs, 0, u5Imm:$U5), 0>,
|
||||
(L4_isub_memoph_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>,
|
||||
Requires<[UseMEMOP]>;
|
||||
|
||||
def : InstAlias<"memw($Rs) &= $Rt",
|
||||
|
|
@ -343,11 +343,11 @@ def : InstAlias<"memw($Rs) -= $Rt",
|
|||
Requires<[UseMEMOP]>;
|
||||
|
||||
def : InstAlias<"memw($Rs) += #$U5",
|
||||
(L4_iadd_memopw_io IntRegs:$Rs, 0, u5Imm:$U5), 0>,
|
||||
(L4_iadd_memopw_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>,
|
||||
Requires<[UseMEMOP]>;
|
||||
|
||||
def : InstAlias<"memw($Rs) -= #$U5",
|
||||
(L4_isub_memopw_io IntRegs:$Rs, 0, u5Imm:$U5), 0>,
|
||||
(L4_isub_memopw_io IntRegs:$Rs, 0, u5_0Imm:$U5), 0>,
|
||||
Requires<[UseMEMOP]>;
|
||||
|
||||
//
|
||||
|
|
|
|||
|
|
@ -92,17 +92,17 @@ class T_CMP <string mnemonic, bits<2> MajOp, bit isNot, Operand ImmOp>
|
|||
let Inst{1-0} = dst;
|
||||
}
|
||||
|
||||
def C2_cmpeqi : T_CMP <"cmp.eq", 0b00, 0, s10Ext>;
|
||||
def C2_cmpgti : T_CMP <"cmp.gt", 0b01, 0, s10Ext>;
|
||||
def C2_cmpgtui : T_CMP <"cmp.gtu", 0b10, 0, u9Ext>;
|
||||
def C2_cmpeqi : T_CMP <"cmp.eq", 0b00, 0, s10_0Ext>;
|
||||
def C2_cmpgti : T_CMP <"cmp.gt", 0b01, 0, s10_0Ext>;
|
||||
def C2_cmpgtui : T_CMP <"cmp.gtu", 0b10, 0, u9_0Ext>;
|
||||
|
||||
class T_CMP_pat <InstHexagon MI, PatFrag OpNode, PatLeaf ImmPred>
|
||||
: Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)),
|
||||
(MI IntRegs:$src1, ImmPred:$src2)>;
|
||||
|
||||
def : T_CMP_pat <C2_cmpeqi, seteq, s10ImmPred>;
|
||||
def : T_CMP_pat <C2_cmpgti, setgt, s10ImmPred>;
|
||||
def : T_CMP_pat <C2_cmpgtui, setugt, u9ImmPred>;
|
||||
def : T_CMP_pat <C2_cmpeqi, seteq, s10_0ImmPred>;
|
||||
def : T_CMP_pat <C2_cmpgti, setgt, s10_0ImmPred>;
|
||||
def : T_CMP_pat <C2_cmpgtui, setugt, u9_0ImmPred>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// ALU32/ALU +
|
||||
|
|
@ -330,10 +330,10 @@ def: Pat<(i32 (select (i1 PredRegs:$Pu), (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))),
|
|||
let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
|
||||
isExtentSigned = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 1,
|
||||
AddedComplexity = 75 in
|
||||
def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8Ext:$s8, s8Imm:$S8),
|
||||
def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8_0Ext:$s8, s8_0Imm:$S8),
|
||||
"$Rdd = combine(#$s8, #$S8)",
|
||||
[(set (i64 DoubleRegs:$Rdd),
|
||||
(i64 (HexagonCOMBINE(i32 s32ImmPred:$s8), (i32 s8ImmPred:$S8))))]> {
|
||||
(i64 (HexagonCOMBINE(i32 s32_0ImmPred:$s8), (i32 s8_0ImmPred:$S8))))]> {
|
||||
bits<5> Rdd;
|
||||
bits<8> s8;
|
||||
bits<8> S8;
|
||||
|
|
@ -352,7 +352,7 @@ def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8Ext:$s8, s8Imm:$S8),
|
|||
let hasNewValue = 1, hasSideEffects = 0 in
|
||||
class T_Addri_Pred <bit PredNot, bit PredNew>
|
||||
: ALU32_ri <(outs IntRegs:$Rd),
|
||||
(ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
|
||||
(ins PredRegs:$Pu, IntRegs:$Rs, s8_0Ext:$s8),
|
||||
!if(PredNot, "if (!$Pu", "if ($Pu")#!if(PredNew,".new) $Rd = ",
|
||||
") $Rd = ")#"add($Rs, #$s8)"> {
|
||||
bits<5> Rd;
|
||||
|
|
@ -407,7 +407,7 @@ let isExtendable = 1, isExtentSigned = 1, InputType = "imm" in
|
|||
multiclass Addri_base<string mnemonic, SDNode OpNode> {
|
||||
let CextOpcode = mnemonic, BaseOpcode = mnemonic#_ri in {
|
||||
let opExtendable = 2, opExtentBits = 16, isPredicable = 1, isAdd = 1 in
|
||||
def A2_#NAME : T_Addri<s16Ext>;
|
||||
def A2_#NAME : T_Addri<s16_0Ext>;
|
||||
|
||||
let opExtendable = 3, opExtentBits = 8, isPredicated = 1 in {
|
||||
defm A2_p#NAME#t : Addri_Pred<mnemonic, 0>;
|
||||
|
|
@ -418,7 +418,7 @@ multiclass Addri_base<string mnemonic, SDNode OpNode> {
|
|||
|
||||
defm addi : Addri_base<"add", add>, ImmRegRel, PredNewRel;
|
||||
|
||||
def: Pat<(i32 (add I32:$Rs, s32ImmPred:$s16)),
|
||||
def: Pat<(i32 (add I32:$Rs, s32_0ImmPred:$s16)),
|
||||
(i32 (A2_addi I32:$Rs, imm:$s16))>;
|
||||
|
||||
let hasNewValue = 1, hasSideEffects = 0, isPseudo = 1 in
|
||||
|
|
@ -436,9 +436,9 @@ let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 10,
|
|||
InputType = "imm", hasNewValue = 1 in
|
||||
class T_ALU32ri_logical <string mnemonic, SDNode OpNode, bits<2> MinOp>
|
||||
: ALU32_ri <(outs IntRegs:$Rd),
|
||||
(ins IntRegs:$Rs, s10Ext:$s10),
|
||||
(ins IntRegs:$Rs, s10_0Ext:$s10),
|
||||
"$Rd = "#mnemonic#"($Rs, #$s10)" ,
|
||||
[(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s32ImmPred:$s10))]> {
|
||||
[(set (i32 IntRegs:$Rd), (OpNode (i32 IntRegs:$Rs), s32_0ImmPred:$s10))]> {
|
||||
bits<5> Rd;
|
||||
bits<5> Rs;
|
||||
bits<10> s10;
|
||||
|
|
@ -461,7 +461,7 @@ def A2_andir : T_ALU32ri_logical<"and", and, 0b00>, ImmRegRel;
|
|||
// Rd32=sub(#s10,Rs32)
|
||||
let isExtendable = 1, CextOpcode = "sub", opExtendable = 1, isExtentSigned = 1,
|
||||
opExtentBits = 10, InputType = "imm", hasNewValue = 1, hasSideEffects = 0 in
|
||||
def A2_subri: ALU32_ri <(outs IntRegs:$Rd), (ins s10Ext:$s10, IntRegs:$Rs),
|
||||
def A2_subri: ALU32_ri <(outs IntRegs:$Rd), (ins s10_0Ext:$s10, IntRegs:$Rs),
|
||||
"$Rd = sub(#$s10, $Rs)", []>, ImmRegRel {
|
||||
bits<5> Rd;
|
||||
bits<10> s10;
|
||||
|
|
@ -483,7 +483,7 @@ def A2_nop: ALU32Inst <(outs), (ins), "nop" > {
|
|||
let Inst{27-24} = 0b1111;
|
||||
}
|
||||
|
||||
def: Pat<(sub s32ImmPred:$s10, IntRegs:$Rs),
|
||||
def: Pat<(sub s32_0ImmPred:$s10, IntRegs:$Rs),
|
||||
(A2_subri imm:$s10, IntRegs:$Rs)>;
|
||||
|
||||
// Rd = not(Rs) gets mapped to Rd=sub(#-1, Rs).
|
||||
|
|
@ -492,7 +492,7 @@ def: Pat<(not (i32 IntRegs:$src1)),
|
|||
|
||||
let hasSideEffects = 0, hasNewValue = 1 in
|
||||
class T_tfr16<bit isHi>
|
||||
: ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16Imm:$u16),
|
||||
: ALU32Inst <(outs IntRegs:$Rx), (ins IntRegs:$src1, u16_0Imm:$u16),
|
||||
"$Rx"#!if(isHi, ".h", ".l")#" = #$u16",
|
||||
[], "$src1 = $Rx" > {
|
||||
bits<5> Rx;
|
||||
|
|
@ -601,7 +601,7 @@ let InputType = "imm", isExtendable = 1, isExtentSigned = 1, opExtentBits = 12,
|
|||
isMoveImm = 1, opExtendable = 2, BaseOpcode = "TFRI", CextOpcode = "TFR",
|
||||
hasSideEffects = 0, isPredicated = 1, hasNewValue = 1 in
|
||||
class T_TFRI_Pred<bit PredNot, bit PredNew>
|
||||
: ALU32_ri<(outs IntRegs:$Rd), (ins PredRegs:$Pu, s12Ext:$s12),
|
||||
: ALU32_ri<(outs IntRegs:$Rd), (ins PredRegs:$Pu, s12_0Ext:$s12),
|
||||
"if ("#!if(PredNot,"!","")#"$Pu"#!if(PredNew,".new","")#") $Rd = #$s12",
|
||||
[], "", ALU32_2op_tc_1_SLOT0123>, ImmRegRel, PredNewRel {
|
||||
let isPredicatedFalse = PredNot;
|
||||
|
|
@ -630,8 +630,8 @@ let InputType = "imm", isExtendable = 1, isExtentSigned = 1,
|
|||
CextOpcode = "TFR", BaseOpcode = "TFRI", hasNewValue = 1, opNewValue = 0,
|
||||
isAsCheapAsAMove = 1 , opExtendable = 1, opExtentBits = 16, isMoveImm = 1,
|
||||
isPredicated = 0, isPredicable = 1, isReMaterializable = 1 in
|
||||
def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16Ext:$s16), "$Rd = #$s16",
|
||||
[(set (i32 IntRegs:$Rd), s32ImmPred:$s16)], "", ALU32_2op_tc_1_SLOT0123>,
|
||||
def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16_0Ext:$s16), "$Rd = #$s16",
|
||||
[(set (i32 IntRegs:$Rd), s32_0ImmPred:$s16)], "", ALU32_2op_tc_1_SLOT0123>,
|
||||
ImmRegRel, PredRel {
|
||||
bits<5> Rd;
|
||||
bits<16> s16;
|
||||
|
|
@ -649,17 +649,17 @@ defm A2_tfrp : TFR64_base<"TFR64">, PredNewRel;
|
|||
// Assembler mapped
|
||||
let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
|
||||
isAsmParserOnly = 1 in
|
||||
def A2_tfrpi : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
|
||||
def A2_tfrpi : ALU64_rr<(outs DoubleRegs:$dst), (ins s8_0Imm64:$src1),
|
||||
"$dst = #$src1",
|
||||
[(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
|
||||
[(set (i64 DoubleRegs:$dst), s8_0Imm64Pred:$src1)]>;
|
||||
|
||||
// TODO: see if this instruction can be deleted..
|
||||
let isExtendable = 1, opExtendable = 1, opExtentBits = 6,
|
||||
isAsmParserOnly = 1 in {
|
||||
def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u64Imm:$src1),
|
||||
def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u64_0Imm:$src1),
|
||||
"$dst = #$src1">;
|
||||
def TFRI64_V2_ext : ALU64_rr<(outs DoubleRegs:$dst),
|
||||
(ins s8Ext:$src1, s8Imm:$src2),
|
||||
(ins s8_0Ext:$src1, s8_0Imm:$src2),
|
||||
"$dst = combine(##$src1, #$src2)">;
|
||||
}
|
||||
|
||||
|
|
@ -692,27 +692,27 @@ class T_MUX1 <bit MajOp, dag ins, string AsmStr>
|
|||
}
|
||||
|
||||
let opExtendable = 2 in
|
||||
def C2_muxri : T_MUX1<0b1, (ins PredRegs:$Pu, s8Ext:$s8, IntRegs:$Rs),
|
||||
def C2_muxri : T_MUX1<0b1, (ins PredRegs:$Pu, s8_0Ext:$s8, IntRegs:$Rs),
|
||||
"$Rd = mux($Pu, #$s8, $Rs)">;
|
||||
|
||||
let opExtendable = 3 in
|
||||
def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
|
||||
def C2_muxir : T_MUX1<0b0, (ins PredRegs:$Pu, IntRegs:$Rs, s8_0Ext:$s8),
|
||||
"$Rd = mux($Pu, $Rs, #$s8)">;
|
||||
|
||||
def : Pat<(i32 (select I1:$Pu, s32ImmPred:$s8, I32:$Rs)),
|
||||
(C2_muxri I1:$Pu, s32ImmPred:$s8, I32:$Rs)>;
|
||||
def : Pat<(i32 (select I1:$Pu, s32_0ImmPred:$s8, I32:$Rs)),
|
||||
(C2_muxri I1:$Pu, s32_0ImmPred:$s8, I32:$Rs)>;
|
||||
|
||||
def : Pat<(i32 (select I1:$Pu, I32:$Rs, s32ImmPred:$s8)),
|
||||
(C2_muxir I1:$Pu, I32:$Rs, s32ImmPred:$s8)>;
|
||||
def : Pat<(i32 (select I1:$Pu, I32:$Rs, s32_0ImmPred:$s8)),
|
||||
(C2_muxir I1:$Pu, I32:$Rs, s32_0ImmPred:$s8)>;
|
||||
|
||||
// C2_muxii: Scalar mux immediates.
|
||||
let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1,
|
||||
opExtentBits = 8, opExtendable = 2 in
|
||||
def C2_muxii: ALU32Inst <(outs IntRegs:$Rd),
|
||||
(ins PredRegs:$Pu, s8Ext:$s8, s8Imm:$S8),
|
||||
(ins PredRegs:$Pu, s8_0Ext:$s8, s8_0Imm:$S8),
|
||||
"$Rd = mux($Pu, #$s8, #$S8)" ,
|
||||
[(set (i32 IntRegs:$Rd),
|
||||
(i32 (select I1:$Pu, s32ImmPred:$s8, s8ImmPred:$S8)))] > {
|
||||
(i32 (select I1:$Pu, s32_0ImmPred:$s8, s8_0ImmPred:$S8)))] > {
|
||||
bits<5> Rd;
|
||||
bits<2> Pu;
|
||||
bits<8> s8;
|
||||
|
|
@ -1019,10 +1019,10 @@ def: T_vcmp_pat<A2_vcmpwgtu, setugt, v2i32>;
|
|||
// transform it to cmp.gt subtracting 1 from the immediate.
|
||||
let isPseudo = 1 in {
|
||||
def C2_cmpgei: ALU32Inst <
|
||||
(outs PredRegs:$Pd), (ins IntRegs:$Rs, s8Ext:$s8),
|
||||
(outs PredRegs:$Pd), (ins IntRegs:$Rs, s8_0Ext:$s8),
|
||||
"$Pd = cmp.ge($Rs, #$s8)">;
|
||||
def C2_cmpgeui: ALU32Inst <
|
||||
(outs PredRegs:$Pd), (ins IntRegs:$Rs, u8Ext:$s8),
|
||||
(outs PredRegs:$Pd), (ins IntRegs:$Rs, u8_0Ext:$s8),
|
||||
"$Pd = cmp.geu($Rs, #$s8)">;
|
||||
}
|
||||
|
||||
|
|
@ -2721,12 +2721,12 @@ class T_MType_mpy_ri <bit isNeg, Operand ImmOp, list<dag> pattern>
|
|||
}
|
||||
|
||||
let isExtendable = 1, opExtentBits = 8, opExtendable = 2 in
|
||||
def M2_mpysip : T_MType_mpy_ri <0, u8Ext,
|
||||
[(set (i32 IntRegs:$Rd), (mul IntRegs:$Rs, u32ImmPred:$u8))]>;
|
||||
def M2_mpysip : T_MType_mpy_ri <0, u8_0Ext,
|
||||
[(set (i32 IntRegs:$Rd), (mul IntRegs:$Rs, u32_0ImmPred:$u8))]>;
|
||||
|
||||
def M2_mpysin : T_MType_mpy_ri <1, u8Imm,
|
||||
def M2_mpysin : T_MType_mpy_ri <1, u8_0Imm,
|
||||
[(set (i32 IntRegs:$Rd), (ineg (mul IntRegs:$Rs,
|
||||
u8ImmPred:$u8)))]>;
|
||||
u8_0ImmPred:$u8)))]>;
|
||||
|
||||
// Assember mapped to M2_mpyi
|
||||
let isAsmParserOnly = 1 in
|
||||
|
|
@ -2741,10 +2741,10 @@ def M2_mpyui : MInst<(outs IntRegs:$dst),
|
|||
let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
|
||||
CextOpcode = "mpyi", InputType = "imm", hasNewValue = 1,
|
||||
isAsmParserOnly = 1 in
|
||||
def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
|
||||
def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9_0Ext:$src2),
|
||||
"$dst = mpyi($src1, #$src2)",
|
||||
[(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
|
||||
s32ImmPred:$src2))]>, ImmRegRel;
|
||||
s32_0ImmPred:$src2))]>, ImmRegRel;
|
||||
|
||||
let hasNewValue = 1, isExtendable = 1, opExtentBits = 8, opExtendable = 3,
|
||||
InputType = "imm" in
|
||||
|
|
@ -2793,9 +2793,9 @@ class T_MType_acc_rr <string mnemonic, bits<3> MajOp, bits<3> MinOp,
|
|||
}
|
||||
|
||||
let CextOpcode = "MPYI_acc", Itinerary = M_tc_3x_SLOT23 in {
|
||||
def M2_macsip : T_MType_acc_ri <"+= mpyi", 0b010, u8Ext,
|
||||
def M2_macsip : T_MType_acc_ri <"+= mpyi", 0b010, u8_0Ext,
|
||||
[(set (i32 IntRegs:$dst),
|
||||
(add (mul IntRegs:$src2, u32ImmPred:$src3),
|
||||
(add (mul IntRegs:$src2, u32_0ImmPred:$src3),
|
||||
IntRegs:$src1))]>, ImmRegRel;
|
||||
|
||||
def M2_maci : T_MType_acc_rr <"+= mpyi", 0b000, 0b000, 0,
|
||||
|
|
@ -2806,9 +2806,9 @@ let CextOpcode = "MPYI_acc", Itinerary = M_tc_3x_SLOT23 in {
|
|||
|
||||
let CextOpcode = "ADD_acc" in {
|
||||
let isExtentSigned = 1 in
|
||||
def M2_accii : T_MType_acc_ri <"+= add", 0b100, s8Ext,
|
||||
def M2_accii : T_MType_acc_ri <"+= add", 0b100, s8_0Ext,
|
||||
[(set (i32 IntRegs:$dst),
|
||||
(add (add (i32 IntRegs:$src2), s32ImmPred:$src3),
|
||||
(add (add (i32 IntRegs:$src2), s32_0ImmPred:$src3),
|
||||
(i32 IntRegs:$src1)))]>, ImmRegRel;
|
||||
|
||||
def M2_acci : T_MType_acc_rr <"+= add", 0b000, 0b001, 0,
|
||||
|
|
@ -2819,13 +2819,13 @@ let CextOpcode = "ADD_acc" in {
|
|||
|
||||
let CextOpcode = "SUB_acc" in {
|
||||
let isExtentSigned = 1 in
|
||||
def M2_naccii : T_MType_acc_ri <"-= add", 0b101, s8Ext>, ImmRegRel;
|
||||
def M2_naccii : T_MType_acc_ri <"-= add", 0b101, s8_0Ext>, ImmRegRel;
|
||||
|
||||
def M2_nacci : T_MType_acc_rr <"-= add", 0b100, 0b001, 0>, ImmRegRel;
|
||||
}
|
||||
|
||||
let Itinerary = M_tc_3x_SLOT23 in
|
||||
def M2_macsin : T_MType_acc_ri <"-= mpyi", 0b011, u8Ext>;
|
||||
def M2_macsin : T_MType_acc_ri <"-= mpyi", 0b011, u8_0Ext>;
|
||||
|
||||
def M2_xor_xacc : T_MType_acc_rr < "^= xor", 0b100, 0b011, 0>;
|
||||
def M2_subacc : T_MType_acc_rr <"+= sub", 0b000, 0b011, 1>;
|
||||
|
|
@ -2840,9 +2840,9 @@ class T_MType_acc_pat2 <InstHexagon MI, SDNode firstOp, SDNode secOp>
|
|||
(MI IntRegs:$src1, IntRegs:$src2, IntRegs:$src3)>;
|
||||
|
||||
def : T_MType_acc_pat2 <M2_xor_xacc, xor, xor>;
|
||||
def : T_MType_acc_pat1 <M2_macsin, mul, sub, u32ImmPred>;
|
||||
def : T_MType_acc_pat1 <M2_macsin, mul, sub, u32_0ImmPred>;
|
||||
|
||||
def : T_MType_acc_pat1 <M2_naccii, add, sub, s32ImmPred>;
|
||||
def : T_MType_acc_pat1 <M2_naccii, add, sub, s32_0ImmPred>;
|
||||
def : T_MType_acc_pat2 <M2_nacci, add, sub>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
@ -4017,7 +4017,7 @@ class T_S2op_2 <string mnemonic, bits<4> RegTyBits, RegisterClass RCOut,
|
|||
RegisterClass RCIn, bits<3> MajOp, bits<3> MinOp,
|
||||
bit isSat, bit isRnd, list<dag> pattern = []>
|
||||
: SInst <(outs RCOut:$dst),
|
||||
(ins RCIn:$src, u5Imm:$u5),
|
||||
(ins RCIn:$src, u5_0Imm:$u5),
|
||||
"$dst = "#mnemonic#"($src, #$u5)"#!if(isSat, ":sat", "")
|
||||
#!if(isRnd, ":rnd", ""),
|
||||
pattern, "", S_2op_tc_2_SLOT23> {
|
||||
|
|
@ -4052,7 +4052,7 @@ class T_S2op_2_ii <string mnemonic, bits<3> MajOp, bits<3> MinOp,
|
|||
class T_S2op_shift <string mnemonic, bits<3> MajOp, bits<3> MinOp, SDNode OpNd>
|
||||
: T_S2op_2_ii <mnemonic, MajOp, MinOp, 0, 0,
|
||||
[(set (i32 IntRegs:$dst), (OpNd (i32 IntRegs:$src),
|
||||
(u5ImmPred:$u5)))]>;
|
||||
(u5_0ImmPred:$u5)))]>;
|
||||
|
||||
// Vector arithmetic shift right by immediate with truncate and pack
|
||||
def S2_asr_i_svw_trun : T_S2op_2_id <"vasrw", 0b110, 0b010>;
|
||||
|
|
@ -4073,7 +4073,7 @@ def S2_asr_i_r_rnd : T_S2op_2_ii <"asr", 0b010, 0b000, 0, 1>;
|
|||
|
||||
let isAsmParserOnly = 1 in
|
||||
def S2_asr_i_r_rnd_goodsyntax
|
||||
: SInst <(outs IntRegs:$dst), (ins IntRegs:$src, u5Imm:$u5),
|
||||
: SInst <(outs IntRegs:$dst), (ins IntRegs:$src, u5_0Imm:$u5),
|
||||
"$dst = asrrnd($src, #$u5)",
|
||||
[], "", S_2op_tc_1_SLOT23>;
|
||||
|
||||
|
|
@ -4081,10 +4081,10 @@ let isAsmParserOnly = 1 in
|
|||
def A2_not: ALU32_rr<(outs IntRegs:$dst),(ins IntRegs:$src),
|
||||
"$dst = not($src)">;
|
||||
|
||||
def: Pat<(i32 (sra (i32 (add (i32 (sra I32:$src1, u5ImmPred:$src2)),
|
||||
def: Pat<(i32 (sra (i32 (add (i32 (sra I32:$src1, u5_0ImmPred:$src2)),
|
||||
(i32 1))),
|
||||
(i32 1))),
|
||||
(S2_asr_i_r_rnd IntRegs:$src1, u5ImmPred:$src2)>;
|
||||
(S2_asr_i_r_rnd IntRegs:$src1, u5_0ImmPred:$src2)>;
|
||||
|
||||
class T_S2op_3<string opc, bits<2>MajOp, bits<3>minOp, bits<1> sat = 0>
|
||||
: SInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss),
|
||||
|
|
@ -4187,7 +4187,7 @@ def: Pat<(i32 (cttz (not I32:$Rs))), (S2_ct1 I32:$Rs)>;
|
|||
|
||||
let hasSideEffects = 0, hasNewValue = 1 in
|
||||
class T_SCT_BIT_IMM<string MnOp, bits<3> MinOp>
|
||||
: SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, u5Imm:$u5),
|
||||
: SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, u5_0Imm:$u5),
|
||||
"$Rd = "#MnOp#"($Rs, #$u5)", [], "", S_2op_tc_1_SLOT23> {
|
||||
bits<5> Rd;
|
||||
bits<5> Rs;
|
||||
|
|
@ -4223,12 +4223,12 @@ def S2_clrbit_r : T_SCT_BIT_REG<"clrbit", 0b01>;
|
|||
def S2_setbit_r : T_SCT_BIT_REG<"setbit", 0b00>;
|
||||
def S2_togglebit_r : T_SCT_BIT_REG<"togglebit", 0b10>;
|
||||
|
||||
def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, u5ImmPred:$u5)))),
|
||||
(S2_clrbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
|
||||
def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
|
||||
(S2_setbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
|
||||
def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, u5ImmPred:$u5))),
|
||||
(S2_togglebit_i IntRegs:$Rs, u5ImmPred:$u5)>;
|
||||
def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, u5_0ImmPred:$u5)))),
|
||||
(S2_clrbit_i IntRegs:$Rs, u5_0ImmPred:$u5)>;
|
||||
def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, u5_0ImmPred:$u5))),
|
||||
(S2_setbit_i IntRegs:$Rs, u5_0ImmPred:$u5)>;
|
||||
def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, u5_0ImmPred:$u5))),
|
||||
(S2_togglebit_i IntRegs:$Rs, u5_0ImmPred:$u5)>;
|
||||
def: Pat<(i32 (and (i32 IntRegs:$Rs), (not (shl 1, (i32 IntRegs:$Rt))))),
|
||||
(S2_clrbit_r IntRegs:$Rs, IntRegs:$Rt)>;
|
||||
def: Pat<(i32 (or (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
|
||||
|
|
@ -4240,7 +4240,7 @@ def: Pat<(i32 (xor (i32 IntRegs:$Rs), (shl 1, (i32 IntRegs:$Rt)))),
|
|||
|
||||
let hasSideEffects = 0 in
|
||||
class T_TEST_BIT_IMM<string MnOp, bits<3> MajOp>
|
||||
: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5Imm:$u5),
|
||||
: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u5_0Imm:$u5),
|
||||
"$Pd = "#MnOp#"($Rs, #$u5)",
|
||||
[], "", S_2op_tc_2early_SLOT23> {
|
||||
bits<2> Pd;
|
||||
|
|
@ -4275,8 +4275,8 @@ def S2_tstbit_i : T_TEST_BIT_IMM<"tstbit", 0b000>;
|
|||
def S2_tstbit_r : T_TEST_BIT_REG<"tstbit", 0>;
|
||||
|
||||
let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
|
||||
def: Pat<(i1 (setne (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
|
||||
(S2_tstbit_i IntRegs:$Rs, u5ImmPred:$u5)>;
|
||||
def: Pat<(i1 (setne (and (shl 1, u5_0ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
|
||||
(S2_tstbit_i IntRegs:$Rs, u5_0ImmPred:$u5)>;
|
||||
def: Pat<(i1 (setne (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
|
||||
(S2_tstbit_r IntRegs:$Rs, IntRegs:$Rt)>;
|
||||
def: Pat<(i1 (trunc (i32 IntRegs:$Rs))),
|
||||
|
|
@ -4287,7 +4287,7 @@ let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
|
|||
|
||||
let hasSideEffects = 0 in
|
||||
class T_TEST_BITS_IMM<string MnOp, bits<2> MajOp, bit IsNeg>
|
||||
: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u6Imm:$u6),
|
||||
: SInst<(outs PredRegs:$Pd), (ins IntRegs:$Rs, u6_0Imm:$u6),
|
||||
"$Pd = "#MnOp#"($Rs, #$u6)",
|
||||
[], "", S_2op_tc_2early_SLOT23> {
|
||||
bits<2> Pd;
|
||||
|
|
@ -4324,8 +4324,8 @@ def C2_bitsclr : T_TEST_BITS_REG<"bitsclr", 0b10, 0>;
|
|||
def C2_bitsset : T_TEST_BITS_REG<"bitsset", 0b01, 0>;
|
||||
|
||||
let AddedComplexity = 20 in { // Complexity greater than compare reg-imm.
|
||||
def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), u6ImmPred:$u6), 0)),
|
||||
(C2_bitsclri IntRegs:$Rs, u6ImmPred:$u6)>;
|
||||
def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), u6_0ImmPred:$u6), 0)),
|
||||
(C2_bitsclri IntRegs:$Rs, u6_0ImmPred:$u6)>;
|
||||
def: Pat<(i1 (seteq (and (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), 0)),
|
||||
(C2_bitsclr IntRegs:$Rs, IntRegs:$Rt)>;
|
||||
}
|
||||
|
|
@ -4400,7 +4400,7 @@ def C2_pxfer_map: SInst<(outs PredRegs:$dst), (ins PredRegs:$src),
|
|||
// Patterns for loads of i1:
|
||||
def: Pat<(i1 (load AddrFI:$fi)),
|
||||
(C2_tfrrp (L2_loadrub_io AddrFI:$fi, 0))>;
|
||||
def: Pat<(i1 (load (add (i32 IntRegs:$Rs), s32ImmPred:$Off))),
|
||||
def: Pat<(i1 (load (add (i32 IntRegs:$Rs), s32_0ImmPred:$Off))),
|
||||
(C2_tfrrp (L2_loadrub_io IntRegs:$Rs, imm:$Off))>;
|
||||
def: Pat<(i1 (load (i32 IntRegs:$Rs))),
|
||||
(C2_tfrrp (L2_loadrub_io IntRegs:$Rs, 0))>;
|
||||
|
|
@ -4411,7 +4411,7 @@ def I1toI32: OutPatFrag<(ops node:$Rs),
|
|||
def I32toI1: OutPatFrag<(ops node:$Rs),
|
||||
(i1 (C2_tfrrp (i32 $Rs)))>;
|
||||
|
||||
defm: Storexm_pat<store, I1, s32ImmPred, I1toI32, S2_storerb_io>;
|
||||
defm: Storexm_pat<store, I1, s32_0ImmPred, I1toI32, S2_storerb_io>;
|
||||
def: Storexm_simple_pat<store, I1, I1toI32, S2_storerb_io>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
@ -4437,9 +4437,9 @@ class S_2OpInstImm<string Mnemonic, bits<3>MajOp, bits<3>MinOp,
|
|||
}
|
||||
|
||||
class S_2OpInstImmI6<string Mnemonic, SDNode OpNode, bits<3>MinOp>
|
||||
: S_2OpInstImm<Mnemonic, 0b000, MinOp, u6Imm,
|
||||
: S_2OpInstImm<Mnemonic, 0b000, MinOp, u6_0Imm,
|
||||
[(set (i64 DoubleRegs:$dst), (OpNode (i64 DoubleRegs:$src1),
|
||||
u6ImmPred:$src2))]> {
|
||||
u6_0ImmPred:$src2))]> {
|
||||
bits<6> src2;
|
||||
let Inst{13-8} = src2;
|
||||
}
|
||||
|
|
@ -4452,10 +4452,10 @@ def S2_lsr_i_p : S_2OpInstImmI6<"lsr", srl, 0b001>;
|
|||
// Shift left by small amount and add.
|
||||
let AddedComplexity = 100, hasNewValue = 1, hasSideEffects = 0 in
|
||||
def S2_addasl_rrri: SInst <(outs IntRegs:$Rd),
|
||||
(ins IntRegs:$Rt, IntRegs:$Rs, u3Imm:$u3),
|
||||
(ins IntRegs:$Rt, IntRegs:$Rs, u3_0Imm:$u3),
|
||||
"$Rd = addasl($Rt, $Rs, #$u3)" ,
|
||||
[(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rt),
|
||||
(shl (i32 IntRegs:$Rs), u3ImmPred:$u3)))],
|
||||
(shl (i32 IntRegs:$Rs), u3_0ImmPred:$u3)))],
|
||||
"", S_3op_tc_2_SLOT23> {
|
||||
bits<5> Rd;
|
||||
bits<5> Rt;
|
||||
|
|
@ -4519,13 +4519,13 @@ def Y2_barrier : SYSInst<(outs), (ins),
|
|||
let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
|
||||
isPseudo = 1, isCodeGenOnly = 1, hasSideEffects = 0 in {
|
||||
def PS_fi : ALU32_ri<(outs IntRegs:$Rd),
|
||||
(ins IntRegs:$fi, s32Imm:$off), "">;
|
||||
(ins IntRegs:$fi, s32_0Imm:$off), "">;
|
||||
def PS_fia : ALU32_ri<(outs IntRegs:$Rd),
|
||||
(ins IntRegs:$Rs, IntRegs:$fi, s32Imm:$off), "">;
|
||||
(ins IntRegs:$Rs, IntRegs:$fi, s32_0Imm:$off), "">;
|
||||
}
|
||||
|
||||
def: Pat<(orisadd (i32 AddrFI:$Rs), s32ImmPred:$off),
|
||||
(PS_fi (i32 AddrFI:$Rs), s32ImmPred:$off)>;
|
||||
def: Pat<(orisadd (i32 AddrFI:$Rs), s32_0ImmPred:$off),
|
||||
(PS_fi (i32 AddrFI:$Rs), s32_0ImmPred:$off)>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// CRUSER - Type.
|
||||
|
|
@ -4534,7 +4534,7 @@ def: Pat<(orisadd (i32 AddrFI:$Rs), s32ImmPred:$off),
|
|||
let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
|
||||
opExtendable = 0, hasSideEffects = 0 in
|
||||
class LOOP_iBase<string mnemonic, Operand brOp, bit mustExtend = 0>
|
||||
: CRInst<(outs), (ins brOp:$offset, u10Imm:$src2),
|
||||
: CRInst<(outs), (ins brOp:$offset, u10_0Imm:$src2),
|
||||
#mnemonic#"($offset, #$src2)",
|
||||
[], "" , CR_tc_3x_SLOT3> {
|
||||
bits<9> offset;
|
||||
|
|
@ -4606,7 +4606,7 @@ let Defs = [LC0, SA0, P3, USR], hasSideEffects = 0,
|
|||
isExtentSigned = 1, isExtendable = 1, opExtentBits = 9, opExtentAlign = 2,
|
||||
opExtendable = 0, isPredicateLate = 1 in
|
||||
class SPLOOP_iBase<string SP, bits<2> op>
|
||||
: CRInst <(outs), (ins brtarget:$r7_2, u10Imm:$U10),
|
||||
: CRInst <(outs), (ins brtarget:$r7_2, u10_0Imm:$U10),
|
||||
"p3 = sp"#SP#"loop0($r7_2, #$U10)" > {
|
||||
bits<9> r7_2;
|
||||
bits<10> U10;
|
||||
|
|
@ -4747,7 +4747,7 @@ let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
|
|||
hasNewValue = 1, opNewValue = 0 in
|
||||
class REG_IMMED<string RegHalf, bit Rs, bits<3> MajOp, bit MinOp>
|
||||
: ALU32_ri<(outs IntRegs:$dst),
|
||||
(ins u16Imm:$imm_value),
|
||||
(ins u16_0Imm:$imm_value),
|
||||
"$dst"#RegHalf#" = $imm_value", []> {
|
||||
bits<5> dst;
|
||||
bits<32> imm_value;
|
||||
|
|
@ -4774,8 +4774,8 @@ let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in {
|
|||
}
|
||||
|
||||
// Map TLS addressses to A2_tfrsi.
|
||||
def: Pat<(HexagonCONST32 tglobaltlsaddr:$addr), (A2_tfrsi s16Ext:$addr)>;
|
||||
def: Pat<(HexagonCONST32 bbl:$label), (A2_tfrsi s16Ext:$label)>;
|
||||
def: Pat<(HexagonCONST32 tglobaltlsaddr:$addr), (A2_tfrsi s16_0Ext:$addr)>;
|
||||
def: Pat<(HexagonCONST32 bbl:$label), (A2_tfrsi s16_0Ext:$label)>;
|
||||
|
||||
let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
|
||||
isCodeGenOnly = 1 in
|
||||
|
|
@ -4852,19 +4852,19 @@ def: Pat<(add (i1 PredRegs:$src1), -1),
|
|||
(C2_not PredRegs:$src1)>;
|
||||
|
||||
// Map from p0 = pnot(p0); r0 = mux(p0, #i, #j) => r0 = mux(p0, #j, #i).
|
||||
def: Pat<(select (not (i1 PredRegs:$src1)), s8ImmPred:$src2, s32ImmPred:$src3),
|
||||
(C2_muxii PredRegs:$src1, s32ImmPred:$src3, s8ImmPred:$src2)>;
|
||||
def: Pat<(select (not (i1 PredRegs:$src1)), s8_0ImmPred:$src2, s32_0ImmPred:$src3),
|
||||
(C2_muxii PredRegs:$src1, s32_0ImmPred:$src3, s8_0ImmPred:$src2)>;
|
||||
|
||||
// Map from p0 = pnot(p0); r0 = select(p0, #i, r1)
|
||||
// => r0 = C2_muxir(p0, r1, #i)
|
||||
def: Pat<(select (not (i1 PredRegs:$src1)), s32ImmPred:$src2,
|
||||
def: Pat<(select (not (i1 PredRegs:$src1)), s32_0ImmPred:$src2,
|
||||
(i32 IntRegs:$src3)),
|
||||
(C2_muxir PredRegs:$src1, IntRegs:$src3, s32ImmPred:$src2)>;
|
||||
(C2_muxir PredRegs:$src1, IntRegs:$src3, s32_0ImmPred:$src2)>;
|
||||
|
||||
// Map from p0 = pnot(p0); r0 = mux(p0, r1, #i)
|
||||
// => r0 = C2_muxri (p0, #i, r1)
|
||||
def: Pat<(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s32ImmPred:$src3),
|
||||
(C2_muxri PredRegs:$src1, s32ImmPred:$src3, IntRegs:$src2)>;
|
||||
def: Pat<(select (not (i1 PredRegs:$src1)), IntRegs:$src2, s32_0ImmPred:$src3),
|
||||
(C2_muxri PredRegs:$src1, s32_0ImmPred:$src3, IntRegs:$src2)>;
|
||||
|
||||
// Map from p0 = pnot(p0); if (p0) jump => if (!p0) jump.
|
||||
def: Pat<(brcond (not (i1 PredRegs:$src1)), bb:$offset),
|
||||
|
|
@ -4889,9 +4889,9 @@ def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
|
|||
(J2_jumpf (C2_cmpeq (i32 IntRegs:$src1), (i32 IntRegs:$src2)),
|
||||
bb:$offset)>;
|
||||
|
||||
def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10ImmPred:$src2)),
|
||||
def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), s10_0ImmPred:$src2)),
|
||||
bb:$offset),
|
||||
(J2_jumpf (C2_cmpeqi (i32 IntRegs:$src1), s10ImmPred:$src2), bb:$offset)>;
|
||||
(J2_jumpf (C2_cmpeqi (i32 IntRegs:$src1), s10_0ImmPred:$src2), bb:$offset)>;
|
||||
|
||||
def: Pat<(brcond (i1 (setne (i1 PredRegs:$src1), (i1 -1))), bb:$offset),
|
||||
(J2_jumpf PredRegs:$src1, bb:$offset)>;
|
||||
|
|
@ -4900,8 +4900,8 @@ def: Pat<(brcond (i1 (setne (i1 PredRegs:$src1), (i1 0))), bb:$offset),
|
|||
(J2_jumpt PredRegs:$src1, bb:$offset)>;
|
||||
|
||||
// cmp.lt(Rs, Imm) -> !cmp.ge(Rs, Imm) -> !cmp.gt(Rs, Imm-1)
|
||||
def: Pat<(brcond (i1 (setlt (i32 IntRegs:$src1), s8ImmPred:$src2)), bb:$offset),
|
||||
(J2_jumpf (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s8ImmPred:$src2)),
|
||||
def: Pat<(brcond (i1 (setlt (i32 IntRegs:$src1), s8_0ImmPred:$src2)), bb:$offset),
|
||||
(J2_jumpf (C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s8_0ImmPred:$src2)),
|
||||
bb:$offset)>;
|
||||
|
||||
// Map from a 64-bit select to an emulated 64-bit mux.
|
||||
|
|
@ -4929,8 +4929,8 @@ def: Pat<(i1 (trunc (i64 DoubleRegs:$src))),
|
|||
|
||||
// rs <= rt -> !(rs > rt).
|
||||
let AddedComplexity = 30 in
|
||||
def: Pat<(i1 (setle (i32 IntRegs:$src1), s32ImmPred:$src2)),
|
||||
(C2_not (C2_cmpgti IntRegs:$src1, s32ImmPred:$src2))>;
|
||||
def: Pat<(i1 (setle (i32 IntRegs:$src1), s32_0ImmPred:$src2)),
|
||||
(C2_not (C2_cmpgti IntRegs:$src1, s32_0ImmPred:$src2))>;
|
||||
|
||||
// rs <= rt -> !(rs > rt).
|
||||
def : Pat<(i1 (setle (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
|
||||
|
|
@ -4944,8 +4944,8 @@ def: Pat<(i1 (setle (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
|
|||
// Hexagon_TODO: We should improve on this.
|
||||
// rs != rt -> !(rs == rt).
|
||||
let AddedComplexity = 30 in
|
||||
def: Pat<(i1 (setne (i32 IntRegs:$src1), s32ImmPred:$src2)),
|
||||
(C2_not (C2_cmpeqi IntRegs:$src1, s32ImmPred:$src2))>;
|
||||
def: Pat<(i1 (setne (i32 IntRegs:$src1), s32_0ImmPred:$src2)),
|
||||
(C2_not (C2_cmpeqi IntRegs:$src1, s32_0ImmPred:$src2))>;
|
||||
|
||||
// Convert setne back to xor for hexagon since we compute w/ pred registers.
|
||||
def: Pat<(i1 (setne (i1 PredRegs:$src1), (i1 PredRegs:$src2))),
|
||||
|
|
@ -4963,8 +4963,8 @@ def : Pat <(i1 (setge (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
|
|||
|
||||
// cmpge(Rs, Imm) -> cmpgt(Rs, Imm-1)
|
||||
let AddedComplexity = 30 in
|
||||
def: Pat<(i1 (setge (i32 IntRegs:$src1), s32ImmPred:$src2)),
|
||||
(C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s32ImmPred:$src2))>;
|
||||
def: Pat<(i1 (setge (i32 IntRegs:$src1), s32_0ImmPred:$src2)),
|
||||
(C2_cmpgti IntRegs:$src1, (DEC_CONST_SIGNED s32_0ImmPred:$src2))>;
|
||||
|
||||
// Map cmpge(Rss, Rtt) -> !cmpgt(Rtt, Rss).
|
||||
// rss >= rtt -> !(rtt > rss).
|
||||
|
|
@ -4975,21 +4975,21 @@ def: Pat<(i1 (setge (i64 DoubleRegs:$src1), (i64 DoubleRegs:$src2))),
|
|||
// !cmpge(Rs, Imm) -> !cmpgt(Rs, Imm-1).
|
||||
// rs < rt -> !(rs >= rt).
|
||||
let AddedComplexity = 30 in
|
||||
def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32ImmPred:$src2)),
|
||||
def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32_0ImmPred:$src2)),
|
||||
(C2_not (C2_cmpgti IntRegs:$src1,
|
||||
(DEC_CONST_SIGNED s32ImmPred:$src2)))>;
|
||||
(DEC_CONST_SIGNED s32_0ImmPred:$src2)))>;
|
||||
|
||||
// Generate cmpgeu(Rs, #0) -> cmpeq(Rs, Rs)
|
||||
def: Pat<(i1 (setuge (i32 IntRegs:$src1), 0)),
|
||||
(C2_cmpeq IntRegs:$src1, IntRegs:$src1)>;
|
||||
|
||||
// Generate cmpgeu(Rs, #u8) -> cmpgtu(Rs, #u8 -1)
|
||||
def: Pat<(i1 (setuge (i32 IntRegs:$src1), u32ImmPred:$src2)),
|
||||
(C2_cmpgtui IntRegs:$src1, (DEC_CONST_UNSIGNED u32ImmPred:$src2))>;
|
||||
def: Pat<(i1 (setuge (i32 IntRegs:$src1), u32_0ImmPred:$src2)),
|
||||
(C2_cmpgtui IntRegs:$src1, (DEC_CONST_UNSIGNED u32_0ImmPred:$src2))>;
|
||||
|
||||
// Generate cmpgtu(Rs, #u9)
|
||||
def: Pat<(i1 (setugt (i32 IntRegs:$src1), u32ImmPred:$src2)),
|
||||
(C2_cmpgtui IntRegs:$src1, u32ImmPred:$src2)>;
|
||||
def: Pat<(i1 (setugt (i32 IntRegs:$src1), u32_0ImmPred:$src2)),
|
||||
(C2_cmpgtui IntRegs:$src1, u32_0ImmPred:$src2)>;
|
||||
|
||||
// Map from Rs >= Rt -> !(Rt > Rs).
|
||||
// rs >= rt -> !(rt > rs).
|
||||
|
|
@ -5074,18 +5074,18 @@ def HexagonALLOCA : SDNode<"HexagonISD::ALLOCA", SDTHexagonALLOCA,
|
|||
// in MachineFunctionInfo.
|
||||
let Defs = [R29], isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 1 in
|
||||
def PS_alloca: ALU32Inst<(outs IntRegs:$Rd),
|
||||
(ins IntRegs:$Rs, u32Imm:$A), "",
|
||||
(ins IntRegs:$Rs, u32_0Imm:$A), "",
|
||||
[(set (i32 IntRegs:$Rd),
|
||||
(HexagonALLOCA (i32 IntRegs:$Rs), (i32 imm:$A)))]>;
|
||||
|
||||
let isCodeGenOnly = 1, isPseudo = 1, Uses = [R30], hasSideEffects = 0 in
|
||||
def PS_aligna : ALU32Inst<(outs IntRegs:$Rd), (ins u32Imm:$A), "", []>;
|
||||
def PS_aligna : ALU32Inst<(outs IntRegs:$Rd), (ins u32_0Imm:$A), "", []>;
|
||||
|
||||
def HexagonJT: SDNode<"HexagonISD::JT", SDTIntUnaryOp>;
|
||||
def HexagonCP: SDNode<"HexagonISD::CP", SDTIntUnaryOp>;
|
||||
|
||||
def: Pat<(HexagonJT tjumptable:$dst), (A2_tfrsi s16Ext:$dst)>;
|
||||
def: Pat<(HexagonCP tconstpool:$dst), (A2_tfrsi s16Ext:$dst)>;
|
||||
def: Pat<(HexagonJT tjumptable:$dst), (A2_tfrsi s16_0Ext:$dst)>;
|
||||
def: Pat<(HexagonCP tconstpool:$dst), (A2_tfrsi s16_0Ext:$dst)>;
|
||||
|
||||
// XTYPE/SHIFT
|
||||
//
|
||||
|
|
@ -5102,11 +5102,11 @@ let hasNewValue = 1, opNewValue = 0 in
|
|||
class T_shift_imm_acc_r <string opc1, string opc2, SDNode OpNode1,
|
||||
SDNode OpNode2, bits<3> majOp, bits<2> minOp>
|
||||
: SInst_acc<(outs IntRegs:$Rx),
|
||||
(ins IntRegs:$src1, IntRegs:$Rs, u5Imm:$u5),
|
||||
(ins IntRegs:$src1, IntRegs:$Rs, u5_0Imm:$u5),
|
||||
"$Rx "#opc2#opc1#"($Rs, #$u5)",
|
||||
[(set (i32 IntRegs:$Rx),
|
||||
(OpNode2 (i32 IntRegs:$src1),
|
||||
(OpNode1 (i32 IntRegs:$Rs), u5ImmPred:$u5)))],
|
||||
(OpNode1 (i32 IntRegs:$Rs), u5_0ImmPred:$u5)))],
|
||||
"$src1 = $Rx", S_2op_tc_2_SLOT23> {
|
||||
bits<5> Rx;
|
||||
bits<5> Rs;
|
||||
|
|
@ -5159,11 +5159,11 @@ class T_shift_reg_acc_r <string opc1, string opc2, SDNode OpNode1,
|
|||
class T_shift_imm_acc_p <string opc1, string opc2, SDNode OpNode1,
|
||||
SDNode OpNode2, bits<3> majOp, bits<2> minOp>
|
||||
: SInst_acc<(outs DoubleRegs:$Rxx),
|
||||
(ins DoubleRegs:$src1, DoubleRegs:$Rss, u6Imm:$u6),
|
||||
(ins DoubleRegs:$src1, DoubleRegs:$Rss, u6_0Imm:$u6),
|
||||
"$Rxx "#opc2#opc1#"($Rss, #$u6)",
|
||||
[(set (i64 DoubleRegs:$Rxx),
|
||||
(OpNode2 (i64 DoubleRegs:$src1),
|
||||
(OpNode1 (i64 DoubleRegs:$Rss), u6ImmPred:$u6)))],
|
||||
(OpNode1 (i64 DoubleRegs:$Rss), u6_0ImmPred:$u6)))],
|
||||
"$src1 = $Rxx", S_2op_tc_2_SLOT23> {
|
||||
bits<5> Rxx;
|
||||
bits<5> Rss;
|
||||
|
|
@ -5438,7 +5438,7 @@ def S2_vcrotate : T_S3op_shiftVect < "vcrotate", 0b11, 0b00>;
|
|||
let hasSideEffects = 0 in
|
||||
class T_S3op_7 <string mnemonic, bit MajOp >
|
||||
: SInst <(outs DoubleRegs:$Rdd),
|
||||
(ins DoubleRegs:$Rss, DoubleRegs:$Rtt, u3Imm:$u3),
|
||||
(ins DoubleRegs:$Rss, DoubleRegs:$Rtt, u3_0Imm:$u3),
|
||||
"$Rdd = "#mnemonic#"($Rss, $Rtt, #$u3)" ,
|
||||
[], "", S_3op_tc_1_SLOT23 > {
|
||||
bits<5> Rdd;
|
||||
|
|
@ -5495,8 +5495,8 @@ class T_S2op_insert <bits<4> RegTyBits, RegisterClass RC, Operand ImmOp>
|
|||
bit bit13;
|
||||
string ImmOpStr = !cast<string>(ImmOp);
|
||||
|
||||
let bit23 = !if (!eq(ImmOpStr, "u6Imm"), src3{5}, 0);
|
||||
let bit13 = !if (!eq(ImmOpStr, "u6Imm"), src2{5}, 0);
|
||||
let bit23 = !if (!eq(ImmOpStr, "u6_0Imm"), src3{5}, 0);
|
||||
let bit13 = !if (!eq(ImmOpStr, "u6_0Imm"), src2{5}, 0);
|
||||
|
||||
let IClass = 0b1000;
|
||||
|
||||
|
|
@ -5514,13 +5514,13 @@ class T_S2op_insert <bits<4> RegTyBits, RegisterClass RC, Operand ImmOp>
|
|||
// Rx=insert(Rs,#u5,#U5)
|
||||
let hasNewValue = 1 in {
|
||||
def S2_insert_rp : T_S3op_insert <"insert", IntRegs>;
|
||||
def S2_insert : T_S2op_insert <0b1111, IntRegs, u5Imm>;
|
||||
def S2_insert : T_S2op_insert <0b1111, IntRegs, u5_0Imm>;
|
||||
}
|
||||
|
||||
// Rxx=insert(Rss,Rtt)
|
||||
// Rxx=insert(Rss,#u6,#U6)
|
||||
def S2_insertp_rp : T_S3op_insert<"insert", DoubleRegs>;
|
||||
def S2_insertp : T_S2op_insert <0b0011, DoubleRegs, u6Imm>;
|
||||
def S2_insertp : T_S2op_insert <0b0011, DoubleRegs, u6_0Imm>;
|
||||
|
||||
|
||||
def SDTHexagonINSERT:
|
||||
|
|
@ -5533,10 +5533,10 @@ def SDTHexagonINSERTRP:
|
|||
def HexagonINSERT : SDNode<"HexagonISD::INSERT", SDTHexagonINSERT>;
|
||||
def HexagonINSERTRP : SDNode<"HexagonISD::INSERTRP", SDTHexagonINSERTRP>;
|
||||
|
||||
def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, u5ImmPred:$u1, u5ImmPred:$u2),
|
||||
(S2_insert I32:$Rs, I32:$Rt, u5ImmPred:$u1, u5ImmPred:$u2)>;
|
||||
def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, u6ImmPred:$u1, u6ImmPred:$u2),
|
||||
(S2_insertp I64:$Rs, I64:$Rt, u6ImmPred:$u1, u6ImmPred:$u2)>;
|
||||
def: Pat<(HexagonINSERT I32:$Rs, I32:$Rt, u5_0ImmPred:$u1, u5_0ImmPred:$u2),
|
||||
(S2_insert I32:$Rs, I32:$Rt, u5_0ImmPred:$u1, u5_0ImmPred:$u2)>;
|
||||
def: Pat<(HexagonINSERT I64:$Rs, I64:$Rt, u6_0ImmPred:$u1, u6_0ImmPred:$u2),
|
||||
(S2_insertp I64:$Rs, I64:$Rt, u6_0ImmPred:$u1, u6_0ImmPred:$u2)>;
|
||||
def: Pat<(HexagonINSERTRP I32:$Rs, I32:$Rt, I64:$Ru),
|
||||
(S2_insert_rp I32:$Rs, I32:$Rt, I64:$Ru)>;
|
||||
def: Pat<(HexagonINSERTRP I64:$Rs, I64:$Rt, I64:$Ru),
|
||||
|
|
@ -5587,10 +5587,10 @@ class T_S2op_extract <string mnemonic, bits<4> RegTyBits,
|
|||
bit bit13;
|
||||
string ImmOpStr = !cast<string>(ImmOp);
|
||||
|
||||
let bit23 = !if (!eq(ImmOpStr, "u6Imm"), src3{5},
|
||||
let bit23 = !if (!eq(ImmOpStr, "u6_0Imm"), src3{5},
|
||||
!if (!eq(mnemonic, "extractu"), 0, 1));
|
||||
|
||||
let bit13 = !if (!eq(ImmOpStr, "u6Imm"), src2{5}, 0);
|
||||
let bit13 = !if (!eq(ImmOpStr, "u6_0Imm"), src2{5}, 0);
|
||||
|
||||
let IClass = 0b1000;
|
||||
|
||||
|
|
@ -5609,13 +5609,13 @@ class T_S2op_extract <string mnemonic, bits<4> RegTyBits,
|
|||
// Rdd=extractu(Rss,Rtt)
|
||||
// Rdd=extractu(Rss,#u6,#U6)
|
||||
def S2_extractup_rp : T_S3op_64 < "extractu", 0b00, 0b000, 0>;
|
||||
def S2_extractup : T_S2op_extract <"extractu", 0b0001, DoubleRegs, u6Imm>;
|
||||
def S2_extractup : T_S2op_extract <"extractu", 0b0001, DoubleRegs, u6_0Imm>;
|
||||
|
||||
// Rd=extractu(Rs,Rtt)
|
||||
// Rd=extractu(Rs,#u5,#U5)
|
||||
let hasNewValue = 1 in {
|
||||
def S2_extractu_rp : T_S3op_extract<"extractu", 0b00>;
|
||||
def S2_extractu : T_S2op_extract <"extractu", 0b1101, IntRegs, u5Imm>;
|
||||
def S2_extractu : T_S2op_extract <"extractu", 0b1101, IntRegs, u5_0Imm>;
|
||||
}
|
||||
|
||||
def SDTHexagonEXTRACTU:
|
||||
|
|
@ -5628,18 +5628,18 @@ def SDTHexagonEXTRACTURP:
|
|||
def HexagonEXTRACTU : SDNode<"HexagonISD::EXTRACTU", SDTHexagonEXTRACTU>;
|
||||
def HexagonEXTRACTURP : SDNode<"HexagonISD::EXTRACTURP", SDTHexagonEXTRACTURP>;
|
||||
|
||||
def: Pat<(HexagonEXTRACTU I32:$src1, u5ImmPred:$src2, u5ImmPred:$src3),
|
||||
(S2_extractu I32:$src1, u5ImmPred:$src2, u5ImmPred:$src3)>;
|
||||
def: Pat<(HexagonEXTRACTU I64:$src1, u6ImmPred:$src2, u6ImmPred:$src3),
|
||||
(S2_extractup I64:$src1, u6ImmPred:$src2, u6ImmPred:$src3)>;
|
||||
def: Pat<(HexagonEXTRACTU I32:$src1, u5_0ImmPred:$src2, u5_0ImmPred:$src3),
|
||||
(S2_extractu I32:$src1, u5_0ImmPred:$src2, u5_0ImmPred:$src3)>;
|
||||
def: Pat<(HexagonEXTRACTU I64:$src1, u6_0ImmPred:$src2, u6_0ImmPred:$src3),
|
||||
(S2_extractup I64:$src1, u6_0ImmPred:$src2, u6_0ImmPred:$src3)>;
|
||||
def: Pat<(HexagonEXTRACTURP I32:$src1, I64:$src2),
|
||||
(S2_extractu_rp I32:$src1, I64:$src2)>;
|
||||
def: Pat<(HexagonEXTRACTURP I64:$src1, I64:$src2),
|
||||
(S2_extractup_rp I64:$src1, I64:$src2)>;
|
||||
|
||||
// Change the sign of the immediate for Rd=-mpyi(Rs,#u8)
|
||||
def: Pat<(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
|
||||
(M2_mpysin IntRegs:$src1, u8ImmPred:$src2)>;
|
||||
def: Pat<(mul (i32 IntRegs:$src1), (ineg n8_0ImmPred:$src2)),
|
||||
(M2_mpysin IntRegs:$src1, u8_0ImmPred:$src2)>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// :raw for of tableindx[bdhw] insns
|
||||
|
|
@ -5648,7 +5648,7 @@ def: Pat<(mul (i32 IntRegs:$src1), (ineg n8ImmPred:$src2)),
|
|||
let hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
|
||||
class tableidxRaw<string OpStr, bits<2>MinOp>
|
||||
: SInst <(outs IntRegs:$Rx),
|
||||
(ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, s6Imm:$S6),
|
||||
(ins IntRegs:$_dst_, IntRegs:$Rs, u4_0Imm:$u4, s6_0Imm:$S6),
|
||||
"$Rx = "#OpStr#"($Rs, #$u4, #$S6):raw",
|
||||
[], "$Rx = $_dst_" > {
|
||||
bits<5> Rx;
|
||||
|
|
@ -5679,7 +5679,7 @@ def S2_tableidxd : tableidxRaw<"tableidxd", 0b11>;
|
|||
let isPseudo = 1 in
|
||||
class tableidx_goodsyntax <string mnemonic>
|
||||
: SInst <(outs IntRegs:$Rx),
|
||||
(ins IntRegs:$_dst_, IntRegs:$Rs, u4Imm:$u4, u5Imm:$u5),
|
||||
(ins IntRegs:$_dst_, IntRegs:$Rs, u4_0Imm:$u4, u5_0Imm:$u5),
|
||||
"$Rx = "#mnemonic#"($Rs, #$u4, #$u5)",
|
||||
[], "$Rx = $_dst_" >;
|
||||
|
||||
|
|
|
|||
|
|
@ -236,15 +236,15 @@ class T_CMP_ribh<string mnemonic, bits<2> MajOp, bit IsHalf, bit IsComm,
|
|||
let Inst{1-0} = Pd;
|
||||
}
|
||||
|
||||
def A4_cmpbeqi : T_CMP_ribh<"cmpb.eq", 0b00, 0, 1, u8Imm, 0, 0, 8>;
|
||||
def A4_cmpbgti : T_CMP_ribh<"cmpb.gt", 0b01, 0, 0, s8Imm, 0, 1, 8>;
|
||||
def A4_cmpbgtui : T_CMP_ribh<"cmpb.gtu", 0b10, 0, 0, u7Ext, 1, 0, 7>;
|
||||
def A4_cmpheqi : T_CMP_ribh<"cmph.eq", 0b00, 1, 1, s8Ext, 1, 1, 8>;
|
||||
def A4_cmphgti : T_CMP_ribh<"cmph.gt", 0b01, 1, 0, s8Ext, 1, 1, 8>;
|
||||
def A4_cmphgtui : T_CMP_ribh<"cmph.gtu", 0b10, 1, 0, u7Ext, 1, 0, 7>;
|
||||
def A4_cmpbeqi : T_CMP_ribh<"cmpb.eq", 0b00, 0, 1, u8_0Imm, 0, 0, 8>;
|
||||
def A4_cmpbgti : T_CMP_ribh<"cmpb.gt", 0b01, 0, 0, s8_0Imm, 0, 1, 8>;
|
||||
def A4_cmpbgtui : T_CMP_ribh<"cmpb.gtu", 0b10, 0, 0, u7_0Ext, 1, 0, 7>;
|
||||
def A4_cmpheqi : T_CMP_ribh<"cmph.eq", 0b00, 1, 1, s8_0Ext, 1, 1, 8>;
|
||||
def A4_cmphgti : T_CMP_ribh<"cmph.gt", 0b01, 1, 0, s8_0Ext, 1, 1, 8>;
|
||||
def A4_cmphgtui : T_CMP_ribh<"cmph.gtu", 0b10, 1, 0, u7_0Ext, 1, 0, 7>;
|
||||
|
||||
class T_RCMP_EQ_ri<string mnemonic, bit IsNeg>
|
||||
: ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8Ext:$s8),
|
||||
: ALU32_ri<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s8_0Ext:$s8),
|
||||
"$Rd = "#mnemonic#"($Rs, #$s8)", [], "", ALU32_2op_tc_1_SLOT0123>,
|
||||
ImmRegRel {
|
||||
let InputType = "imm";
|
||||
|
|
@ -272,10 +272,10 @@ class T_RCMP_EQ_ri<string mnemonic, bit IsNeg>
|
|||
def A4_rcmpeqi : T_RCMP_EQ_ri<"cmp.eq", 0>;
|
||||
def A4_rcmpneqi : T_RCMP_EQ_ri<"!cmp.eq", 1>;
|
||||
|
||||
def: Pat<(i32 (zext (i1 (seteq (i32 IntRegs:$Rs), s32ImmPred:$s8)))),
|
||||
(A4_rcmpeqi IntRegs:$Rs, s32ImmPred:$s8)>;
|
||||
def: Pat<(i32 (zext (i1 (setne (i32 IntRegs:$Rs), s32ImmPred:$s8)))),
|
||||
(A4_rcmpneqi IntRegs:$Rs, s32ImmPred:$s8)>;
|
||||
def: Pat<(i32 (zext (i1 (seteq (i32 IntRegs:$Rs), s32_0ImmPred:$s8)))),
|
||||
(A4_rcmpeqi IntRegs:$Rs, s32_0ImmPred:$s8)>;
|
||||
def: Pat<(i32 (zext (i1 (setne (i32 IntRegs:$Rs), s32_0ImmPred:$s8)))),
|
||||
(A4_rcmpneqi IntRegs:$Rs, s32_0ImmPred:$s8)>;
|
||||
|
||||
// Preserve the S2_tstbit_r generation
|
||||
def: Pat<(i32 (zext (i1 (setne (i32 (and (i32 (shl 1, (i32 IntRegs:$src2))),
|
||||
|
|
@ -310,26 +310,26 @@ class T_Combine1 <bits<2> MajOp, dag ins, string AsmStr>
|
|||
}
|
||||
|
||||
let opExtendable = 2 in
|
||||
def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8Ext:$s8),
|
||||
def A4_combineri : T_Combine1<0b00, (ins IntRegs:$Rs, s8_0Ext:$s8),
|
||||
"$Rdd = combine($Rs, #$s8)">;
|
||||
|
||||
let opExtendable = 1 in
|
||||
def A4_combineir : T_Combine1<0b01, (ins s8Ext:$s8, IntRegs:$Rs),
|
||||
def A4_combineir : T_Combine1<0b01, (ins s8_0Ext:$s8, IntRegs:$Rs),
|
||||
"$Rdd = combine(#$s8, $Rs)">;
|
||||
|
||||
// The complexity of the combines involving immediates should be greater
|
||||
// than the complexity of the combine with two registers.
|
||||
let AddedComplexity = 50 in {
|
||||
def: Pat<(HexagonCOMBINE IntRegs:$r, s32ImmPred:$i),
|
||||
(A4_combineri IntRegs:$r, s32ImmPred:$i)>;
|
||||
def: Pat<(HexagonCOMBINE IntRegs:$r, s32_0ImmPred:$i),
|
||||
(A4_combineri IntRegs:$r, s32_0ImmPred:$i)>;
|
||||
|
||||
def: Pat<(HexagonCOMBINE s32ImmPred:$i, IntRegs:$r),
|
||||
(A4_combineir s32ImmPred:$i, IntRegs:$r)>;
|
||||
def: Pat<(HexagonCOMBINE s32_0ImmPred:$i, IntRegs:$r),
|
||||
(A4_combineir s32_0ImmPred:$i, IntRegs:$r)>;
|
||||
}
|
||||
|
||||
// A4_combineii: Set two small immediates.
|
||||
let hasSideEffects = 0, isExtendable = 1, opExtentBits = 6, opExtendable = 2 in
|
||||
def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8Imm:$s8, u6Ext:$U6),
|
||||
def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8_0Imm:$s8, u6_0Ext:$U6),
|
||||
"$Rdd = combine(#$s8, #$U6)"> {
|
||||
bits<5> Rdd;
|
||||
bits<8> s8;
|
||||
|
|
@ -346,7 +346,7 @@ def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8Imm:$s8, u6Ext:$U6),
|
|||
// The complexity of the combine with two immediates should be greater than
|
||||
// the complexity of a combine involving a register.
|
||||
let AddedComplexity = 75 in
|
||||
def: Pat<(HexagonCOMBINE s8ImmPred:$s8, u32ImmPred:$u6),
|
||||
def: Pat<(HexagonCOMBINE s8_0ImmPred:$s8, u32_0ImmPred:$u6),
|
||||
(A4_combineii imm:$s8, imm:$u6)>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
@ -397,7 +397,7 @@ let isExtended = 1, opExtendable = 2, opExtentBits = 6, addrMode = AbsoluteSet,
|
|||
hasSideEffects = 0 in
|
||||
class T_LD_abs_set<string mnemonic, RegisterClass RC, bits<4>MajOp>:
|
||||
LDInst<(outs RC:$dst1, IntRegs:$dst2),
|
||||
(ins u6Ext:$addr),
|
||||
(ins u6_0Ext:$addr),
|
||||
"$dst1 = "#mnemonic#"($dst2 = #$addr)",
|
||||
[]> {
|
||||
bits<7> name;
|
||||
|
|
@ -449,7 +449,7 @@ let InputType = "imm", addrMode = BaseLongOffset, isExtended = 1,
|
|||
opExtentBits = 6, opExtendable = 3 in
|
||||
class T_LoadAbsReg <string mnemonic, string CextOp, RegisterClass RC,
|
||||
bits<4> MajOp>
|
||||
: LDInst <(outs RC:$dst), (ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3),
|
||||
: LDInst <(outs RC:$dst), (ins IntRegs:$src1, u2_0Imm:$src2, u6_0Ext:$src3),
|
||||
"$dst = "#mnemonic#"($src1<<#$src2 + #$src3)",
|
||||
[] >, ImmRegShl {
|
||||
bits<5> dst;
|
||||
|
|
@ -498,23 +498,23 @@ def L4_loadrd_ur : T_LoadAbsReg<"memd", "LDrid", DoubleRegs, 0b1110>;
|
|||
|
||||
|
||||
multiclass T_LoadAbsReg_Pat <PatFrag ldOp, InstHexagon MI, ValueType VT = i32> {
|
||||
def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2ImmPred:$src2),
|
||||
def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2_0ImmPred:$src2),
|
||||
(HexagonCONST32 tglobaladdr:$src3)))),
|
||||
(MI IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3)>;
|
||||
(MI IntRegs:$src1, u2_0ImmPred:$src2, tglobaladdr:$src3)>;
|
||||
def : Pat <(VT (ldOp (add IntRegs:$src1,
|
||||
(HexagonCONST32 tglobaladdr:$src2)))),
|
||||
(MI IntRegs:$src1, 0, tglobaladdr:$src2)>;
|
||||
|
||||
def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2ImmPred:$src2),
|
||||
def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2_0ImmPred:$src2),
|
||||
(HexagonCONST32 tconstpool:$src3)))),
|
||||
(MI IntRegs:$src1, u2ImmPred:$src2, tconstpool:$src3)>;
|
||||
(MI IntRegs:$src1, u2_0ImmPred:$src2, tconstpool:$src3)>;
|
||||
def : Pat <(VT (ldOp (add IntRegs:$src1,
|
||||
(HexagonCONST32 tconstpool:$src2)))),
|
||||
(MI IntRegs:$src1, 0, tconstpool:$src2)>;
|
||||
|
||||
def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2ImmPred:$src2),
|
||||
def : Pat <(VT (ldOp (add (shl IntRegs:$src1, u2_0ImmPred:$src2),
|
||||
(HexagonCONST32 tjumptable:$src3)))),
|
||||
(MI IntRegs:$src1, u2ImmPred:$src2, tjumptable:$src3)>;
|
||||
(MI IntRegs:$src1, u2_0ImmPred:$src2, tjumptable:$src3)>;
|
||||
def : Pat <(VT (ldOp (add IntRegs:$src1,
|
||||
(HexagonCONST32 tjumptable:$src2)))),
|
||||
(MI IntRegs:$src1, 0, tjumptable:$src2)>;
|
||||
|
|
@ -538,7 +538,7 @@ defm : T_LoadAbsReg_Pat <load, L4_loadrd_ur, i64>;
|
|||
// base + register offset addressing mode
|
||||
//===----------------------------------------------------------------------===//
|
||||
class T_load_rr <string mnemonic, RegisterClass RC, bits<3> MajOp>:
|
||||
LDInst<(outs RC:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2Imm:$u2),
|
||||
LDInst<(outs RC:$dst), (ins IntRegs:$src1, IntRegs:$src2, u2_0Imm:$u2),
|
||||
"$dst = "#mnemonic#"($src1 + $src2<<#$u2)",
|
||||
[], "", V4LDST_tc_ld_SLOT01>, ImmRegShl, AddrModeRel {
|
||||
bits<5> dst;
|
||||
|
|
@ -565,7 +565,7 @@ let isPredicated = 1 in
|
|||
class T_pload_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
|
||||
bit isNot, bit isPredNew>:
|
||||
LDInst <(outs RC:$dst),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2Imm:$u2),
|
||||
(ins PredRegs:$src1, IntRegs:$src2, IntRegs:$src3, u2_0Imm:$u2),
|
||||
!if(isNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
|
||||
") ")#"$dst = "#mnemonic#"($src2+$src3<<#$u2)",
|
||||
[], "", V4LDST_tc_ld_SLOT01>, AddrModeRel {
|
||||
|
|
@ -635,7 +635,7 @@ defm loadrd : ld_idxd_shl<"memd", "LDrid", DoubleRegs, 0b110>;
|
|||
// register operand.
|
||||
class Loadxs_pat<PatFrag Load, ValueType VT, InstHexagon MI>
|
||||
: Pat<(VT (Load (add (i32 IntRegs:$Rs),
|
||||
(i32 (shl (i32 IntRegs:$Rt), u2ImmPred:$u2))))),
|
||||
(i32 (shl (i32 IntRegs:$Rt), u2_0ImmPred:$u2))))),
|
||||
(VT (MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2))>;
|
||||
|
||||
let AddedComplexity = 40 in {
|
||||
|
|
@ -690,7 +690,7 @@ let isExtended = 1, opExtendable = 1, opExtentBits = 6,
|
|||
class T_ST_absset <string mnemonic, string BaseOp, RegisterClass RC,
|
||||
bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
|
||||
: STInst<(outs IntRegs:$dst),
|
||||
(ins u6Ext:$addr, RC:$src),
|
||||
(ins u6_0Ext:$addr, RC:$src),
|
||||
mnemonic#"($dst = #$addr) = $src"#!if(isHalf, ".h","")>, NewValueRel {
|
||||
bits<5> dst;
|
||||
bits<6> addr;
|
||||
|
|
@ -729,7 +729,7 @@ isExtended = 1, opExtentBits= 6 in
|
|||
class T_ST_absset_nv <string mnemonic, string BaseOp, bits<2> MajOp,
|
||||
MemAccessSize AccessSz >
|
||||
: NVInst <(outs IntRegs:$dst),
|
||||
(ins u6Ext:$addr, IntRegs:$src),
|
||||
(ins u6_0Ext:$addr, IntRegs:$src),
|
||||
mnemonic#"($dst = #$addr) = $src.new">, NewValueRel {
|
||||
bits<5> dst;
|
||||
bits<6> addr;
|
||||
|
|
@ -759,7 +759,7 @@ let isExtended = 1, opExtendable = 2, opExtentBits = 6, InputType = "imm",
|
|||
class T_StoreAbsReg <string mnemonic, string CextOp, RegisterClass RC,
|
||||
bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
|
||||
: STInst<(outs),
|
||||
(ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, RC:$src4),
|
||||
(ins IntRegs:$src1, u2_0Imm:$src2, u6_0Ext:$src3, RC:$src4),
|
||||
mnemonic#"($src1<<#$src2 + #$src3) = $src4"#!if(isHalf, ".h",""),
|
||||
[]>, ImmRegShl, NewValueRel {
|
||||
|
||||
|
|
@ -800,14 +800,14 @@ let AddedComplexity = 40 in
|
|||
multiclass T_StoreAbsReg_Pats <InstHexagon MI, RegisterClass RC, ValueType VT,
|
||||
PatFrag stOp> {
|
||||
def : Pat<(stOp (VT RC:$src4),
|
||||
(add (shl (i32 IntRegs:$src1), u2ImmPred:$src2),
|
||||
u32ImmPred:$src3)),
|
||||
(MI IntRegs:$src1, u2ImmPred:$src2, u32ImmPred:$src3, RC:$src4)>;
|
||||
(add (shl (i32 IntRegs:$src1), u2_0ImmPred:$src2),
|
||||
u32_0ImmPred:$src3)),
|
||||
(MI IntRegs:$src1, u2_0ImmPred:$src2, u32_0ImmPred:$src3, RC:$src4)>;
|
||||
|
||||
def : Pat<(stOp (VT RC:$src4),
|
||||
(add (shl IntRegs:$src1, u2ImmPred:$src2),
|
||||
(add (shl IntRegs:$src1, u2_0ImmPred:$src2),
|
||||
(HexagonCONST32 tglobaladdr:$src3))),
|
||||
(MI IntRegs:$src1, u2ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
|
||||
(MI IntRegs:$src1, u2_0ImmPred:$src2, tglobaladdr:$src3, RC:$src4)>;
|
||||
|
||||
def : Pat<(stOp (VT RC:$src4),
|
||||
(add IntRegs:$src1, (HexagonCONST32 tglobaladdr:$src3))),
|
||||
|
|
@ -824,7 +824,7 @@ let mayStore = 1, isNVStore = 1, isExtended = 1, addrMode = BaseLongOffset,
|
|||
class T_StoreAbsRegNV <string mnemonic, string CextOp, bits<2> MajOp,
|
||||
MemAccessSize AccessSz>
|
||||
: NVInst <(outs ),
|
||||
(ins IntRegs:$src1, u2Imm:$src2, u6Ext:$src3, IntRegs:$src4),
|
||||
(ins IntRegs:$src1, u2_0Imm:$src2, u6_0Ext:$src3, IntRegs:$src4),
|
||||
mnemonic#"($src1<<#$src2 + #$src3) = $src4.new">, NewValueRel {
|
||||
bits<5> src1;
|
||||
bits<2> src2;
|
||||
|
|
@ -856,7 +856,7 @@ def S4_storerinew_ur : T_StoreAbsRegNV <"memw", "STriw", 0b10, WordAccess>;
|
|||
//===----------------------------------------------------------------------===//
|
||||
let isPredicable = 1 in
|
||||
class T_store_rr <string mnemonic, RegisterClass RC, bits<3> MajOp, bit isH>
|
||||
: STInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
|
||||
: STInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2_0Imm:$u2, RC:$Rt),
|
||||
mnemonic#"($Rs + $Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
|
||||
[],"",V4LDST_tc_st_SLOT01>, ImmRegShl, AddrModeRel {
|
||||
|
||||
|
|
@ -887,7 +887,7 @@ let isPredicated = 1 in
|
|||
class T_pstore_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
|
||||
bit isNot, bit isPredNew, bit isH>
|
||||
: STInst <(outs),
|
||||
(ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, RC:$Rt),
|
||||
(ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2_0Imm:$u2, RC:$Rt),
|
||||
|
||||
!if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
|
||||
") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Rt"#!if(isH, ".h",""),
|
||||
|
|
@ -923,7 +923,7 @@ class T_pstore_rr <string mnemonic, RegisterClass RC, bits<3> MajOp,
|
|||
//===----------------------------------------------------------------------===//
|
||||
let isPredicable = 1, isNewValue = 1, opNewValue = 3 in
|
||||
class T_store_new_rr <string mnemonic, bits<2> MajOp> :
|
||||
NVInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
|
||||
NVInst < (outs ), (ins IntRegs:$Rs, IntRegs:$Ru, u2_0Imm:$u2, IntRegs:$Nt),
|
||||
mnemonic#"($Rs + $Ru<<#$u2) = $Nt.new",
|
||||
[],"",V4LDST_tc_st_SLOT0>, ImmRegShl, AddrModeRel {
|
||||
|
||||
|
|
@ -950,7 +950,7 @@ class T_store_new_rr <string mnemonic, bits<2> MajOp> :
|
|||
let isPredicated = 1, isNewValue = 1, opNewValue = 4 in
|
||||
class T_pstore_new_rr <string mnemonic, bits<2> MajOp, bit isNot, bit isPredNew>
|
||||
: NVInst<(outs),
|
||||
(ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2Imm:$u2, IntRegs:$Nt),
|
||||
(ins PredRegs:$Pv, IntRegs:$Rs, IntRegs:$Ru, u2_0Imm:$u2, IntRegs:$Nt),
|
||||
!if(isNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
|
||||
") ")#mnemonic#"($Rs+$Ru<<#$u2) = $Nt.new",
|
||||
[], "", V4LDST_tc_st_SLOT0>, AddrModeRel {
|
||||
|
|
@ -1039,7 +1039,7 @@ let addrMode = BaseRegOffset, InputType = "reg", hasSideEffects = 0 in {
|
|||
|
||||
class Storexs_pat<PatFrag Store, PatFrag Value, InstHexagon MI>
|
||||
: Pat<(Store Value:$Ru, (add (i32 IntRegs:$Rs),
|
||||
(i32 (shl (i32 IntRegs:$Rt), u2ImmPred:$u2)))),
|
||||
(i32 (shl (i32 IntRegs:$Rt), u2_0ImmPred:$u2)))),
|
||||
(MI IntRegs:$Rs, IntRegs:$Rt, imm:$u2, Value:$Ru)>;
|
||||
|
||||
let AddedComplexity = 40 in {
|
||||
|
|
@ -1091,7 +1091,7 @@ let AddedComplexity = 20 in {
|
|||
let isPredicable = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 8,
|
||||
opExtendable = 2 in
|
||||
class T_StoreImm <string mnemonic, Operand OffsetOp, bits<2> MajOp >
|
||||
: STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8Ext:$S8),
|
||||
: STInst <(outs ), (ins IntRegs:$Rs, OffsetOp:$offset, s8_0Ext:$S8),
|
||||
mnemonic#"($Rs+#$offset)=#$S8",
|
||||
[], "", V4LDST_tc_st_SLOT01>,
|
||||
ImmRegRel, PredNewRel {
|
||||
|
|
@ -1120,7 +1120,7 @@ let isPredicated = 1, isExtendable = 1, isExtentSigned = 1, opExtentBits = 6,
|
|||
class T_StoreImm_pred <string mnemonic, Operand OffsetOp, bits<2> MajOp,
|
||||
bit isPredNot, bit isPredNew >
|
||||
: STInst <(outs ),
|
||||
(ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6Ext:$S6),
|
||||
(ins PredRegs:$Pv, IntRegs:$Rs, OffsetOp:$offset, s6_0Ext:$S6),
|
||||
!if(isPredNot, "if (!$Pv", "if ($Pv")#!if(isPredNew, ".new) ",
|
||||
") ")#mnemonic#"($Rs+#$offset)=#$S6",
|
||||
[], "", V4LDST_tc_st_SLOT01>,
|
||||
|
|
@ -1243,19 +1243,19 @@ let AddedComplexity = 40 in {
|
|||
// can still generate the fi# in the base address. If the final offset
|
||||
// is not valid for the instruction, we will replace it with a scratch
|
||||
// register.
|
||||
// def: Storexm_fi_pat <truncstorei8, s32ImmPred, ToImmByte, S4_storeirb_io>;
|
||||
// def: Storexm_fi_pat <truncstorei8, s32_0ImmPred, ToImmByte, S4_storeirb_io>;
|
||||
// def: Storexm_fi_pat <truncstorei16, i16in8ImmPred, ToImmHalf,
|
||||
// S4_storeirh_io>;
|
||||
// def: Storexm_fi_pat <store, i32in8ImmPred, ToImmWord, S4_storeiri_io>;
|
||||
|
||||
// defm: Storexm_fi_add_pat <truncstorei8, s32ImmPred, u6_0ImmPred, ToImmByte,
|
||||
// defm: Storexm_fi_add_pat <truncstorei8, s32_0ImmPred, u6_0ImmPred, ToImmByte,
|
||||
// S4_storeirb_io>;
|
||||
// defm: Storexm_fi_add_pat <truncstorei16, i16in8ImmPred, u6_1ImmPred,
|
||||
// ToImmHalf, S4_storeirh_io>;
|
||||
// defm: Storexm_fi_add_pat <store, i32in8ImmPred, u6_2ImmPred, ToImmWord,
|
||||
// S4_storeiri_io>;
|
||||
|
||||
defm: Storexm_add_pat<truncstorei8, s32ImmPred, u6_0ImmPred, ToImmByte,
|
||||
defm: Storexm_add_pat<truncstorei8, s32_0ImmPred, u6_0ImmPred, ToImmByte,
|
||||
S4_storeirb_io>;
|
||||
defm: Storexm_add_pat<truncstorei16, i16in8ImmPred, u6_1ImmPred, ToImmHalf,
|
||||
S4_storeirh_io>;
|
||||
|
|
@ -1263,9 +1263,9 @@ let AddedComplexity = 40 in {
|
|||
S4_storeiri_io>;
|
||||
}
|
||||
|
||||
def: Storexm_simple_pat<truncstorei8, s32ImmPred, ToImmByte, S4_storeirb_io>;
|
||||
def: Storexm_simple_pat<truncstorei16, s32ImmPred, ToImmHalf, S4_storeirh_io>;
|
||||
def: Storexm_simple_pat<store, s32ImmPred, ToImmWord, S4_storeiri_io>;
|
||||
def: Storexm_simple_pat<truncstorei8, s32_0ImmPred, ToImmByte, S4_storeirb_io>;
|
||||
def: Storexm_simple_pat<truncstorei16, s32_0ImmPred, ToImmHalf, S4_storeirh_io>;
|
||||
def: Storexm_simple_pat<store, s32_0ImmPred, ToImmWord, S4_storeiri_io>;
|
||||
|
||||
// memb(Rx++#s4:0:circ(Mu))=Rt
|
||||
// memb(Rx++I:circ(Mu))=Rt
|
||||
|
|
@ -1700,7 +1700,7 @@ let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 11,
|
|||
class NVJri_template<string mnemonic, bits<3> majOp, bit isNegCond,
|
||||
bit isTak>
|
||||
: NVInst_V4<(outs),
|
||||
(ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset),
|
||||
(ins IntRegs:$src1, u5_0Imm:$src2, brtarget:$offset),
|
||||
"if ("#!if(isNegCond, "!","")#mnemonic#"($src1.new, #$src2)) jump:"
|
||||
#!if(isTak, "t","nt")#" $offset", []> {
|
||||
|
||||
|
|
@ -1829,7 +1829,7 @@ def J4_hintjumpr: JRInst <
|
|||
// PC-relative add
|
||||
let hasNewValue = 1, isExtendable = 1, opExtendable = 1,
|
||||
isExtentSigned = 0, opExtentBits = 6, hasSideEffects = 0, Uses = [PC] in
|
||||
def C4_addipc : CRInst <(outs IntRegs:$Rd), (ins u6Ext:$u6),
|
||||
def C4_addipc : CRInst <(outs IntRegs:$Rd), (ins u6_0Ext:$u6),
|
||||
"$Rd = add(pc, #$u6)", [], "", CR_tc_2_SLOT3 > {
|
||||
bits<5> Rd;
|
||||
bits<6> u6;
|
||||
|
|
@ -1953,10 +1953,10 @@ def S4_parity: ALU64Inst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, IntRegs:$Rt),
|
|||
let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 6,
|
||||
opExtendable = 3 in
|
||||
def S4_addaddi : ALU64Inst <(outs IntRegs:$Rd),
|
||||
(ins IntRegs:$Rs, IntRegs:$Ru, s6Ext:$s6),
|
||||
(ins IntRegs:$Rs, IntRegs:$Ru, s6_0Ext:$s6),
|
||||
"$Rd = add($Rs, add($Ru, #$s6))" ,
|
||||
[(set (i32 IntRegs:$Rd), (add (i32 IntRegs:$Rs),
|
||||
(add (i32 IntRegs:$Ru), s32ImmPred:$s6)))],
|
||||
(add (i32 IntRegs:$Ru), s32_0ImmPred:$s6)))],
|
||||
"", ALU64_tc_2_SLOT23> {
|
||||
bits<5> Rd;
|
||||
bits<5> Rs;
|
||||
|
|
@ -1977,7 +1977,7 @@ def S4_addaddi : ALU64Inst <(outs IntRegs:$Rd),
|
|||
let isExtentSigned = 1, hasSideEffects = 0, hasNewValue = 1, isExtendable = 1,
|
||||
opExtentBits = 6, opExtendable = 2 in
|
||||
def S4_subaddi: ALU64Inst <(outs IntRegs:$Rd),
|
||||
(ins IntRegs:$Rs, s6Ext:$s6, IntRegs:$Ru),
|
||||
(ins IntRegs:$Rs, s6_0Ext:$s6, IntRegs:$Ru),
|
||||
"$Rd = add($Rs, sub(#$s6, $Ru))",
|
||||
[], "", ALU64_tc_2_SLOT23> {
|
||||
bits<5> Rd;
|
||||
|
|
@ -1997,19 +1997,19 @@ def S4_subaddi: ALU64Inst <(outs IntRegs:$Rd),
|
|||
}
|
||||
|
||||
// Rd=add(Rs,sub(#s6,Ru))
|
||||
def: Pat<(add (i32 IntRegs:$src1), (sub s32ImmPred:$src2,
|
||||
def: Pat<(add (i32 IntRegs:$src1), (sub s32_0ImmPred:$src2,
|
||||
(i32 IntRegs:$src3))),
|
||||
(S4_subaddi IntRegs:$src1, s32ImmPred:$src2, IntRegs:$src3)>;
|
||||
(S4_subaddi IntRegs:$src1, s32_0ImmPred:$src2, IntRegs:$src3)>;
|
||||
|
||||
// Rd=sub(add(Rs,#s6),Ru)
|
||||
def: Pat<(sub (add (i32 IntRegs:$src1), s32ImmPred:$src2),
|
||||
def: Pat<(sub (add (i32 IntRegs:$src1), s32_0ImmPred:$src2),
|
||||
(i32 IntRegs:$src3)),
|
||||
(S4_subaddi IntRegs:$src1, s32ImmPred:$src2, IntRegs:$src3)>;
|
||||
(S4_subaddi IntRegs:$src1, s32_0ImmPred:$src2, IntRegs:$src3)>;
|
||||
|
||||
// Rd=add(sub(Rs,Ru),#s6)
|
||||
def: Pat<(add (sub (i32 IntRegs:$src1), (i32 IntRegs:$src3)),
|
||||
(s32ImmPred:$src2)),
|
||||
(S4_subaddi IntRegs:$src1, s32ImmPred:$src2, IntRegs:$src3)>;
|
||||
(s32_0ImmPred:$src2)),
|
||||
(S4_subaddi IntRegs:$src1, s32_0ImmPred:$src2, IntRegs:$src3)>;
|
||||
|
||||
|
||||
// Add or subtract doublewords with carry.
|
||||
|
|
@ -2025,11 +2025,11 @@ def: Pat<(add (sub (i32 IntRegs:$src1), (i32 IntRegs:$src3)),
|
|||
// Rd=extract(Rs,#u5,#U5)
|
||||
|
||||
def S4_extractp_rp : T_S3op_64 < "extract", 0b11, 0b100, 0>;
|
||||
def S4_extractp : T_S2op_extract <"extract", 0b1010, DoubleRegs, u6Imm>;
|
||||
def S4_extractp : T_S2op_extract <"extract", 0b1010, DoubleRegs, u6_0Imm>;
|
||||
|
||||
let hasNewValue = 1 in {
|
||||
def S4_extract_rp : T_S3op_extract<"extract", 0b01>;
|
||||
def S4_extract : T_S2op_extract <"extract", 0b1101, IntRegs, u5Imm>;
|
||||
def S4_extract : T_S2op_extract <"extract", 0b1101, IntRegs, u5_0Imm>;
|
||||
}
|
||||
|
||||
// Complex add/sub halfwords/words
|
||||
|
|
@ -2079,7 +2079,7 @@ def M4_xor_xacc
|
|||
let hasSideEffects = 0 in
|
||||
def S4_vrcrotate
|
||||
: SInst <(outs DoubleRegs:$Rdd),
|
||||
(ins DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
|
||||
(ins DoubleRegs:$Rss, IntRegs:$Rt, u2_0Imm:$u2),
|
||||
"$Rdd = vrcrotate($Rss, $Rt, #$u2)",
|
||||
[], "", S_3op_tc_3x_SLOT23> {
|
||||
bits<5> Rdd;
|
||||
|
|
@ -2103,7 +2103,7 @@ def S4_vrcrotate
|
|||
let hasSideEffects = 0 in
|
||||
def S4_vrcrotate_acc
|
||||
: SInst <(outs DoubleRegs:$Rxx),
|
||||
(ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt, u2Imm:$u2),
|
||||
(ins DoubleRegs:$dst2, DoubleRegs:$Rss, IntRegs:$Rt, u2_0Imm:$u2),
|
||||
"$Rxx += vrcrotate($Rss, $Rt, #$u2)", [],
|
||||
"$dst2 = $Rxx", S_3op_tc_3x_SLOT23> {
|
||||
bits<5> Rxx;
|
||||
|
|
@ -2159,10 +2159,10 @@ let isExtentSigned = 1, hasNewValue = 1, isExtendable = 1, opExtentBits = 10,
|
|||
opExtendable = 3 in
|
||||
def S4_or_andix:
|
||||
ALU64Inst<(outs IntRegs:$Rx),
|
||||
(ins IntRegs:$Ru, IntRegs:$_src_, s10Ext:$s10),
|
||||
(ins IntRegs:$Ru, IntRegs:$_src_, s10_0Ext:$s10),
|
||||
"$Rx = or($Ru, and($_src_, #$s10))" ,
|
||||
[(set (i32 IntRegs:$Rx),
|
||||
(or (i32 IntRegs:$Ru), (and (i32 IntRegs:$_src_), s32ImmPred:$s10)))] ,
|
||||
(or (i32 IntRegs:$Ru), (and (i32 IntRegs:$_src_), s32_0ImmPred:$s10)))] ,
|
||||
"$_src_ = $Rx", ALU64_tc_2_SLOT23> {
|
||||
bits<5> Rx;
|
||||
bits<5> Ru;
|
||||
|
|
@ -2304,10 +2304,10 @@ let isExtentSigned = 1, InputType = "imm", hasNewValue = 1, isExtendable = 1,
|
|||
opExtentBits = 10, opExtendable = 3 in
|
||||
class T_CompOR <string mnemonic, bits<2> MajOp, SDNode OpNode>
|
||||
: MInst_acc <(outs IntRegs:$Rx),
|
||||
(ins IntRegs:$src1, IntRegs:$Rs, s10Ext:$s10),
|
||||
(ins IntRegs:$src1, IntRegs:$Rs, s10_0Ext:$s10),
|
||||
"$Rx |= "#mnemonic#"($Rs, #$s10)",
|
||||
[(set (i32 IntRegs:$Rx), (or (i32 IntRegs:$src1),
|
||||
(OpNode (i32 IntRegs:$Rs), s32ImmPred:$s10)))],
|
||||
(OpNode (i32 IntRegs:$Rs), s32_0ImmPred:$s10)))],
|
||||
"$src1 = $Rx", ALU64_tc_2_SLOT23>, ImmRegRel {
|
||||
bits<5> Rx;
|
||||
bits<5> Rs;
|
||||
|
|
@ -2392,7 +2392,7 @@ def: Pat<(i64 (cttz (not I64:$Rss))), (Zext64 (S2_ct1p I64:$Rss))>;
|
|||
|
||||
|
||||
let hasSideEffects = 0, hasNewValue = 1 in
|
||||
def S4_clbaddi : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s6Imm:$s6),
|
||||
def S4_clbaddi : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s6_0Imm:$s6),
|
||||
"$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
|
||||
bits<5> Rs;
|
||||
bits<5> Rd;
|
||||
|
|
@ -2407,7 +2407,7 @@ def S4_clbaddi : SInst<(outs IntRegs:$Rd), (ins IntRegs:$Rs, s6Imm:$s6),
|
|||
}
|
||||
|
||||
let hasSideEffects = 0, hasNewValue = 1 in
|
||||
def S4_clbpaddi : SInst<(outs IntRegs:$Rd), (ins DoubleRegs:$Rs, s6Imm:$s6),
|
||||
def S4_clbpaddi : SInst<(outs IntRegs:$Rd), (ins DoubleRegs:$Rs, s6_0Imm:$s6),
|
||||
"$Rd = add(clb($Rs), #$s6)", [], "", S_2op_tc_2_SLOT23> {
|
||||
bits<5> Rs;
|
||||
bits<5> Rd;
|
||||
|
|
@ -2427,8 +2427,8 @@ def S4_ntstbit_i : T_TEST_BIT_IMM<"!tstbit", 0b001>;
|
|||
def S4_ntstbit_r : T_TEST_BIT_REG<"!tstbit", 1>;
|
||||
|
||||
let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm.
|
||||
def: Pat<(i1 (seteq (and (shl 1, u5ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
|
||||
(S4_ntstbit_i (i32 IntRegs:$Rs), u5ImmPred:$u5)>;
|
||||
def: Pat<(i1 (seteq (and (shl 1, u5_0ImmPred:$u5), (i32 IntRegs:$Rs)), 0)),
|
||||
(S4_ntstbit_i (i32 IntRegs:$Rs), u5_0ImmPred:$u5)>;
|
||||
def: Pat<(i1 (seteq (and (shl 1, (i32 IntRegs:$Rt)), (i32 IntRegs:$Rs)), 0)),
|
||||
(S4_ntstbit_r (i32 IntRegs:$Rs), (i32 IntRegs:$Rt))>;
|
||||
}
|
||||
|
|
@ -2454,8 +2454,8 @@ def C4_nbitsclri : T_TEST_BITS_IMM<"!bitsclr", 0b10, 1>;
|
|||
// complexity that would make them preferable, and if they were actually used
|
||||
// instead of cmpb/cmph, they would result in a compare against register that
|
||||
// is loaded with the byte/half mask (i.e. 0xFF or 0xFFFF).
|
||||
def: Pat<(i1 (setne (and I32:$Rs, u6ImmPred:$u6), 0)),
|
||||
(C4_nbitsclri I32:$Rs, u6ImmPred:$u6)>;
|
||||
def: Pat<(i1 (setne (and I32:$Rs, u6_0ImmPred:$u6), 0)),
|
||||
(C4_nbitsclri I32:$Rs, u6_0ImmPred:$u6)>;
|
||||
def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), 0)),
|
||||
(C4_nbitsclr I32:$Rs, I32:$Rt)>;
|
||||
def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)),
|
||||
|
|
@ -2473,11 +2473,11 @@ def: Pat<(i1 (setne (and I32:$Rs, I32:$Rt), I32:$Rt)),
|
|||
|
||||
let hasNewValue = 1, isExtendable = 1, opExtentBits = 6, opExtendable = 1 in
|
||||
def M4_mpyri_addi : MInst<(outs IntRegs:$Rd),
|
||||
(ins u6Ext:$u6, IntRegs:$Rs, u6Imm:$U6),
|
||||
(ins u6_0Ext:$u6, IntRegs:$Rs, u6_0Imm:$U6),
|
||||
"$Rd = add(#$u6, mpyi($Rs, #$U6))" ,
|
||||
[(set (i32 IntRegs:$Rd),
|
||||
(add (mul (i32 IntRegs:$Rs), u6ImmPred:$U6),
|
||||
u32ImmPred:$u6))] ,"",ALU64_tc_3x_SLOT23> {
|
||||
(add (mul (i32 IntRegs:$Rs), u6_0ImmPred:$U6),
|
||||
u32_0ImmPred:$u6))] ,"",ALU64_tc_3x_SLOT23> {
|
||||
bits<5> Rd;
|
||||
bits<6> u6;
|
||||
bits<5> Rs;
|
||||
|
|
@ -2499,10 +2499,10 @@ def M4_mpyri_addi : MInst<(outs IntRegs:$Rd),
|
|||
let CextOpcode = "ADD_MPY", InputType = "imm", hasNewValue = 1,
|
||||
isExtendable = 1, opExtentBits = 6, opExtendable = 1 in
|
||||
def M4_mpyrr_addi : MInst <(outs IntRegs:$Rd),
|
||||
(ins u6Ext:$u6, IntRegs:$Rs, IntRegs:$Rt),
|
||||
(ins u6_0Ext:$u6, IntRegs:$Rs, IntRegs:$Rt),
|
||||
"$Rd = add(#$u6, mpyi($Rs, $Rt))" ,
|
||||
[(set (i32 IntRegs:$Rd),
|
||||
(add (mul (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), u32ImmPred:$u6))],
|
||||
(add (mul (i32 IntRegs:$Rs), (i32 IntRegs:$Rt)), u32_0ImmPred:$u6))],
|
||||
"", ALU64_tc_3x_SLOT23>, ImmRegRel {
|
||||
bits<5> Rd;
|
||||
bits<6> u6;
|
||||
|
|
@ -2552,8 +2552,8 @@ def M4_mpyri_addr_u2 : T_AddMpy<0b0, u6_2ImmPred,
|
|||
|
||||
let isExtendable = 1, opExtentBits = 6, opExtendable = 3,
|
||||
CextOpcode = "ADD_MPY", InputType = "imm" in
|
||||
def M4_mpyri_addr : T_AddMpy<0b1, u32ImmPred,
|
||||
(ins IntRegs:$src1, IntRegs:$src3, u6Ext:$src2)>, ImmRegRel;
|
||||
def M4_mpyri_addr : T_AddMpy<0b1, u32_0ImmPred,
|
||||
(ins IntRegs:$src1, IntRegs:$src3, u6_0Ext:$src2)>, ImmRegRel;
|
||||
|
||||
// Rx=add(Ru,mpyi(Rx,Rs))
|
||||
let CextOpcode = "ADD_MPY", InputType = "reg", hasNewValue = 1 in
|
||||
|
|
@ -2657,19 +2657,19 @@ def: T_vcmp_pat<A4_vcmpbgt, setgt, v8i8>;
|
|||
let AsmString = "$Pd = any8(vcmpb.eq($Rss, $Rtt))" in
|
||||
def A4_vcmpbeq_any : T_vcmp <"any8(vcmpb.gt", 0b1000>;
|
||||
|
||||
def A4_vcmpbeqi : T_vcmpImm <"vcmpb.eq", 0b00, 0b00, u8Imm>;
|
||||
def A4_vcmpbgti : T_vcmpImm <"vcmpb.gt", 0b01, 0b00, s8Imm>;
|
||||
def A4_vcmpbgtui : T_vcmpImm <"vcmpb.gtu", 0b10, 0b00, u7Imm>;
|
||||
def A4_vcmpbeqi : T_vcmpImm <"vcmpb.eq", 0b00, 0b00, u8_0Imm>;
|
||||
def A4_vcmpbgti : T_vcmpImm <"vcmpb.gt", 0b01, 0b00, s8_0Imm>;
|
||||
def A4_vcmpbgtui : T_vcmpImm <"vcmpb.gtu", 0b10, 0b00, u7_0Imm>;
|
||||
|
||||
// Vector compare halfwords
|
||||
def A4_vcmpheqi : T_vcmpImm <"vcmph.eq", 0b00, 0b01, s8Imm>;
|
||||
def A4_vcmphgti : T_vcmpImm <"vcmph.gt", 0b01, 0b01, s8Imm>;
|
||||
def A4_vcmphgtui : T_vcmpImm <"vcmph.gtu", 0b10, 0b01, u7Imm>;
|
||||
def A4_vcmpheqi : T_vcmpImm <"vcmph.eq", 0b00, 0b01, s8_0Imm>;
|
||||
def A4_vcmphgti : T_vcmpImm <"vcmph.gt", 0b01, 0b01, s8_0Imm>;
|
||||
def A4_vcmphgtui : T_vcmpImm <"vcmph.gtu", 0b10, 0b01, u7_0Imm>;
|
||||
|
||||
// Vector compare words
|
||||
def A4_vcmpweqi : T_vcmpImm <"vcmpw.eq", 0b00, 0b10, s8Imm>;
|
||||
def A4_vcmpwgti : T_vcmpImm <"vcmpw.gt", 0b01, 0b10, s8Imm>;
|
||||
def A4_vcmpwgtui : T_vcmpImm <"vcmpw.gtu", 0b10, 0b10, u7Imm>;
|
||||
def A4_vcmpweqi : T_vcmpImm <"vcmpw.eq", 0b00, 0b10, s8_0Imm>;
|
||||
def A4_vcmpwgti : T_vcmpImm <"vcmpw.gt", 0b01, 0b10, s8_0Imm>;
|
||||
def A4_vcmpwgtui : T_vcmpImm <"vcmpw.gtu", 0b10, 0b10, u7_0Imm>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// XTYPE/SHIFT +
|
||||
|
|
@ -2683,7 +2683,7 @@ let isExtendable = 1, opExtendable = 1, isExtentSigned = 0, opExtentBits = 8,
|
|||
hasNewValue = 1, opNewValue = 0 in
|
||||
class T_S4_ShiftOperate<string MnOp, string MnSh, bit asl_lsr,
|
||||
bits<2> MajOp, InstrItinClass Itin>
|
||||
: MInst_acc<(outs IntRegs:$Rd), (ins u8Ext:$u8, IntRegs:$Rx, u5Imm:$U5),
|
||||
: MInst_acc<(outs IntRegs:$Rd), (ins u8_0Ext:$u8, IntRegs:$Rx, u5_0Imm:$U5),
|
||||
"$Rd = "#MnOp#"(#$u8, "#MnSh#"($Rx, #$U5))",
|
||||
[], "$Rd = $Rx", Itin> {
|
||||
|
||||
|
|
@ -2715,8 +2715,8 @@ defm S4_ori : T_ShiftOperate<"or", 0b01, ALU64_tc_1_SLOT23>;
|
|||
defm S4_subi : T_ShiftOperate<"sub", 0b11, ALU64_tc_1_SLOT23>;
|
||||
|
||||
class T_Shift_CommOp_pat<InstHexagon MI, SDNode Op, SDNode ShOp>
|
||||
: Pat<(Op (ShOp IntRegs:$Rx, u5ImmPred:$U5), u32ImmPred:$u8),
|
||||
(MI u32ImmPred:$u8, IntRegs:$Rx, u5ImmPred:$U5)>;
|
||||
: Pat<(Op (ShOp IntRegs:$Rx, u5_0ImmPred:$U5), u32_0ImmPred:$u8),
|
||||
(MI u32_0ImmPred:$u8, IntRegs:$Rx, u5_0ImmPred:$U5)>;
|
||||
|
||||
let AddedComplexity = 200 in {
|
||||
def : T_Shift_CommOp_pat <S4_addi_asl_ri, add, shl>;
|
||||
|
|
@ -2731,21 +2731,21 @@ let AddedComplexity = 30 in {
|
|||
}
|
||||
|
||||
class T_Shift_Op_pat<InstHexagon MI, SDNode Op, SDNode ShOp>
|
||||
: Pat<(Op u32ImmPred:$u8, (ShOp IntRegs:$Rx, u5ImmPred:$U5)),
|
||||
(MI u32ImmPred:$u8, IntRegs:$Rx, u5ImmPred:$U5)>;
|
||||
: Pat<(Op u32_0ImmPred:$u8, (ShOp IntRegs:$Rx, u5_0ImmPred:$U5)),
|
||||
(MI u32_0ImmPred:$u8, IntRegs:$Rx, u5_0ImmPred:$U5)>;
|
||||
|
||||
def : T_Shift_Op_pat <S4_subi_asl_ri, sub, shl>;
|
||||
def : T_Shift_Op_pat <S4_subi_lsr_ri, sub, srl>;
|
||||
|
||||
let AddedComplexity = 200 in {
|
||||
def: Pat<(add addrga:$addr, (shl I32:$src2, u5ImmPred:$src3)),
|
||||
(S4_addi_asl_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
|
||||
def: Pat<(add addrga:$addr, (srl I32:$src2, u5ImmPred:$src3)),
|
||||
(S4_addi_lsr_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
|
||||
def: Pat<(sub addrga:$addr, (shl I32:$src2, u5ImmPred:$src3)),
|
||||
(S4_subi_asl_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
|
||||
def: Pat<(sub addrga:$addr, (srl I32:$src2, u5ImmPred:$src3)),
|
||||
(S4_subi_lsr_ri addrga:$addr, IntRegs:$src2, u5ImmPred:$src3)>;
|
||||
def: Pat<(add addrga:$addr, (shl I32:$src2, u5_0ImmPred:$src3)),
|
||||
(S4_addi_asl_ri addrga:$addr, IntRegs:$src2, u5_0ImmPred:$src3)>;
|
||||
def: Pat<(add addrga:$addr, (srl I32:$src2, u5_0ImmPred:$src3)),
|
||||
(S4_addi_lsr_ri addrga:$addr, IntRegs:$src2, u5_0ImmPred:$src3)>;
|
||||
def: Pat<(sub addrga:$addr, (shl I32:$src2, u5_0ImmPred:$src3)),
|
||||
(S4_subi_asl_ri addrga:$addr, IntRegs:$src2, u5_0ImmPred:$src3)>;
|
||||
def: Pat<(sub addrga:$addr, (srl I32:$src2, u5_0ImmPred:$src3)),
|
||||
(S4_subi_lsr_ri addrga:$addr, IntRegs:$src2, u5_0ImmPred:$src3)>;
|
||||
}
|
||||
|
||||
// Vector conditional negate
|
||||
|
|
@ -2836,9 +2836,9 @@ def A4_vrminuw : T_S3op_6 < "vrminuw", 0b110, 1>;
|
|||
|
||||
// Shift an immediate left by register amount.
|
||||
let hasNewValue = 1, hasSideEffects = 0 in
|
||||
def S4_lsli: SInst <(outs IntRegs:$Rd), (ins s6Imm:$s6, IntRegs:$Rt),
|
||||
def S4_lsli: SInst <(outs IntRegs:$Rd), (ins s6_0Imm:$s6, IntRegs:$Rt),
|
||||
"$Rd = lsl(#$s6, $Rt)" ,
|
||||
[(set (i32 IntRegs:$Rd), (shl s6ImmPred:$s6,
|
||||
[(set (i32 IntRegs:$Rd), (shl s6_0ImmPred:$s6,
|
||||
(i32 IntRegs:$Rt)))],
|
||||
"", S_3op_tc_1_SLOT23> {
|
||||
bits<5> Rd;
|
||||
|
|
@ -2863,12 +2863,12 @@ def S4_lsli: SInst <(outs IntRegs:$Rd), (ins s6Imm:$s6, IntRegs:$Rt),
|
|||
// MEMOP
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def m5Imm8Pred : PatLeaf<(i32 imm), [{
|
||||
def m5_0Imm8Pred : PatLeaf<(i32 imm), [{
|
||||
int8_t v = (int8_t)N->getSExtValue();
|
||||
return v > -32 && v <= -1;
|
||||
}]>;
|
||||
|
||||
def m5Imm16Pred : PatLeaf<(i32 imm), [{
|
||||
def m5_0Imm16Pred : PatLeaf<(i32 imm), [{
|
||||
int16_t v = (int16_t)N->getSExtValue();
|
||||
return v > -32 && v <= -1;
|
||||
}]>;
|
||||
|
|
@ -2966,7 +2966,7 @@ class MemOp_rr_base <string opc, bits<2> opcBits, Operand ImmOp,
|
|||
class MemOp_ri_base <string opc, bits<2> opcBits, Operand ImmOp,
|
||||
string memOp, bits<2> memOpBits> :
|
||||
MEMInst_V4 <(outs),
|
||||
(ins IntRegs:$base, ImmOp:$offset, u5Imm:$delta),
|
||||
(ins IntRegs:$base, ImmOp:$offset, u5_0Imm:$delta),
|
||||
opc#"($base+#$offset)"#memOp#"#$delta"
|
||||
#!if(memOpBits{1},")", ""), // clrbit, setbit - include ')'
|
||||
[]>,
|
||||
|
|
@ -3163,63 +3163,63 @@ multiclass Memopxi_pat<PatFrag Load, PatFrag Store, PatFrag ImmPred,
|
|||
|
||||
let AddedComplexity = 200 in {
|
||||
// add imm
|
||||
defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, u5ImmPred,
|
||||
defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred,
|
||||
/*anyext*/ IdImm, L4_iadd_memopb_io>;
|
||||
defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, u5ImmPred,
|
||||
defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred,
|
||||
/*sext*/ IdImm, L4_iadd_memopb_io>;
|
||||
defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, u5ImmPred,
|
||||
defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, u5_0ImmPred,
|
||||
/*zext*/ IdImm, L4_iadd_memopb_io>;
|
||||
defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5ImmPred,
|
||||
defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred,
|
||||
/*anyext*/ IdImm, L4_iadd_memoph_io>;
|
||||
defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5ImmPred,
|
||||
defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred,
|
||||
/*sext*/ IdImm, L4_iadd_memoph_io>;
|
||||
defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5ImmPred,
|
||||
defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, u5_0ImmPred,
|
||||
/*zext*/ IdImm, L4_iadd_memoph_io>;
|
||||
defm: Memopxi_pat<load, store, u6_2ImmPred, add, u5ImmPred, IdImm,
|
||||
defm: Memopxi_pat<load, store, u6_2ImmPred, add, u5_0ImmPred, IdImm,
|
||||
L4_iadd_memopw_io>;
|
||||
defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, m5Imm8Pred,
|
||||
defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred,
|
||||
/*anyext*/ NegImm8, L4_iadd_memopb_io>;
|
||||
defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, m5Imm8Pred,
|
||||
defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred,
|
||||
/*sext*/ NegImm8, L4_iadd_memopb_io>;
|
||||
defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, m5Imm8Pred,
|
||||
defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, m5_0Imm8Pred,
|
||||
/*zext*/ NegImm8, L4_iadd_memopb_io>;
|
||||
defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, m5Imm16Pred,
|
||||
defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred,
|
||||
/*anyext*/ NegImm16, L4_iadd_memoph_io>;
|
||||
defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, m5Imm16Pred,
|
||||
defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred,
|
||||
/*sext*/ NegImm16, L4_iadd_memoph_io>;
|
||||
defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, m5Imm16Pred,
|
||||
defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, m5_0Imm16Pred,
|
||||
/*zext*/ NegImm16, L4_iadd_memoph_io>;
|
||||
defm: Memopxi_pat<load, store, u6_2ImmPred, sub, m5ImmPred, NegImm32,
|
||||
defm: Memopxi_pat<load, store, u6_2ImmPred, sub, m5_0ImmPred, NegImm32,
|
||||
L4_iadd_memopw_io>;
|
||||
|
||||
// sub imm
|
||||
defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, u5ImmPred,
|
||||
defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred,
|
||||
/*anyext*/ IdImm, L4_isub_memopb_io>;
|
||||
defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, u5ImmPred,
|
||||
defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred,
|
||||
/*sext*/ IdImm, L4_isub_memopb_io>;
|
||||
defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, u5ImmPred,
|
||||
defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, sub, u5_0ImmPred,
|
||||
/*zext*/ IdImm, L4_isub_memopb_io>;
|
||||
defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, u5ImmPred,
|
||||
defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred,
|
||||
/*anyext*/ IdImm, L4_isub_memoph_io>;
|
||||
defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, u5ImmPred,
|
||||
defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred,
|
||||
/*sext*/ IdImm, L4_isub_memoph_io>;
|
||||
defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, u5ImmPred,
|
||||
defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, sub, u5_0ImmPred,
|
||||
/*zext*/ IdImm, L4_isub_memoph_io>;
|
||||
defm: Memopxi_pat<load, store, u6_2ImmPred, sub, u5ImmPred, IdImm,
|
||||
defm: Memopxi_pat<load, store, u6_2ImmPred, sub, u5_0ImmPred, IdImm,
|
||||
L4_isub_memopw_io>;
|
||||
defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, m5Imm8Pred,
|
||||
defm: Memopxi_pat<extloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred,
|
||||
/*anyext*/ NegImm8, L4_isub_memopb_io>;
|
||||
defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, m5Imm8Pred,
|
||||
defm: Memopxi_pat<sextloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred,
|
||||
/*sext*/ NegImm8, L4_isub_memopb_io>;
|
||||
defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, m5Imm8Pred,
|
||||
defm: Memopxi_pat<zextloadi8, truncstorei8, u6_0ImmPred, add, m5_0Imm8Pred,
|
||||
/*zext*/ NegImm8, L4_isub_memopb_io>;
|
||||
defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, m5Imm16Pred,
|
||||
defm: Memopxi_pat<extloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred,
|
||||
/*anyext*/ NegImm16, L4_isub_memoph_io>;
|
||||
defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, add, m5Imm16Pred,
|
||||
defm: Memopxi_pat<sextloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred,
|
||||
/*sext*/ NegImm16, L4_isub_memoph_io>;
|
||||
defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, add, m5Imm16Pred,
|
||||
defm: Memopxi_pat<zextloadi16, truncstorei16, u6_1ImmPred, add, m5_0Imm16Pred,
|
||||
/*zext*/ NegImm16, L4_isub_memoph_io>;
|
||||
defm: Memopxi_pat<load, store, u6_2ImmPred, add, m5ImmPred, NegImm32,
|
||||
defm: Memopxi_pat<load, store, u6_2ImmPred, add, m5_0ImmPred, NegImm32,
|
||||
L4_isub_memopw_io>;
|
||||
|
||||
// clrbit imm
|
||||
|
|
@ -3271,27 +3271,27 @@ let AddedComplexity = 200 in {
|
|||
// Pd=cmpb.eq(Rs,#u8)
|
||||
|
||||
// p=!cmp.eq(r1,#s10)
|
||||
def C4_cmpneqi : T_CMP <"cmp.eq", 0b00, 1, s10Ext>;
|
||||
def C4_cmpltei : T_CMP <"cmp.gt", 0b01, 1, s10Ext>;
|
||||
def C4_cmplteui : T_CMP <"cmp.gtu", 0b10, 1, u9Ext>;
|
||||
def C4_cmpneqi : T_CMP <"cmp.eq", 0b00, 1, s10_0Ext>;
|
||||
def C4_cmpltei : T_CMP <"cmp.gt", 0b01, 1, s10_0Ext>;
|
||||
def C4_cmplteui : T_CMP <"cmp.gtu", 0b10, 1, u9_0Ext>;
|
||||
|
||||
def : T_CMP_pat <C4_cmpneqi, setne, s32ImmPred>;
|
||||
def : T_CMP_pat <C4_cmpltei, setle, s32ImmPred>;
|
||||
def : T_CMP_pat <C4_cmplteui, setule, u9ImmPred>;
|
||||
def : T_CMP_pat <C4_cmpneqi, setne, s32_0ImmPred>;
|
||||
def : T_CMP_pat <C4_cmpltei, setle, s32_0ImmPred>;
|
||||
def : T_CMP_pat <C4_cmplteui, setule, u9_0ImmPred>;
|
||||
|
||||
// rs <= rt -> !(rs > rt).
|
||||
/*
|
||||
def: Pat<(i1 (setle (i32 IntRegs:$src1), s32ImmPred:$src2)),
|
||||
(C2_not (C2_cmpgti IntRegs:$src1, s32ImmPred:$src2))>;
|
||||
// (C4_cmpltei IntRegs:$src1, s32ImmPred:$src2)>;
|
||||
def: Pat<(i1 (setle (i32 IntRegs:$src1), s32_0ImmPred:$src2)),
|
||||
(C2_not (C2_cmpgti IntRegs:$src1, s32_0ImmPred:$src2))>;
|
||||
// (C4_cmpltei IntRegs:$src1, s32_0ImmPred:$src2)>;
|
||||
*/
|
||||
// Map cmplt(Rs, Imm) -> !cmpgt(Rs, Imm-1).
|
||||
def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32ImmPred:$src2)),
|
||||
(C4_cmpltei IntRegs:$src1, (DEC_CONST_SIGNED s32ImmPred:$src2))>;
|
||||
def: Pat<(i1 (setlt (i32 IntRegs:$src1), s32_0ImmPred:$src2)),
|
||||
(C4_cmpltei IntRegs:$src1, (DEC_CONST_SIGNED s32_0ImmPred:$src2))>;
|
||||
|
||||
// rs != rt -> !(rs == rt).
|
||||
def: Pat<(i1 (setne (i32 IntRegs:$src1), s32ImmPred:$src2)),
|
||||
(C4_cmpneqi IntRegs:$src1, s32ImmPred:$src2)>;
|
||||
def: Pat<(i1 (setne (i32 IntRegs:$src1), s32_0ImmPred:$src2)),
|
||||
(C4_cmpneqi IntRegs:$src1, s32_0ImmPred:$src2)>;
|
||||
|
||||
// SDNode for converting immediate C to C-1.
|
||||
def DEC_CONST_BYTE : SDNodeXForm<imm, [{
|
||||
|
|
@ -3318,9 +3318,9 @@ def DEC_CONST_BYTE : SDNodeXForm<imm, [{
|
|||
// retval = (c-48) < 10 ? 1 : 0;
|
||||
let AddedComplexity = 139 in
|
||||
def: Pat<(i32 (zext (i1 (setult (i32 (and (i32 IntRegs:$src1), 255)),
|
||||
u7StrictPosImmPred:$src2)))),
|
||||
u7_0StrictPosImmPred:$src2)))),
|
||||
(C2_muxii (A4_cmpbgtui IntRegs:$src1,
|
||||
(DEC_CONST_BYTE u7StrictPosImmPred:$src2)),
|
||||
(DEC_CONST_BYTE u7_0StrictPosImmPred:$src2)),
|
||||
0, 1)>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
@ -3480,7 +3480,7 @@ class T_StoreAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
|
|||
let hasSideEffects = 0, isPredicated = 1, opExtentBits = 6, opExtendable = 1 in
|
||||
class T_StoreAbs_Pred <string mnemonic, RegisterClass RC, bits<2> MajOp,
|
||||
bit isHalf, bit isNot, bit isNew>
|
||||
: STInst<(outs), (ins PredRegs:$src1, u32MustExt:$absaddr, RC: $src2),
|
||||
: STInst<(outs), (ins PredRegs:$src1, u32_0MustExt:$absaddr, RC: $src2),
|
||||
!if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
|
||||
") ")#mnemonic#"(#$absaddr) = $src2"#!if(isHalf, ".h",""),
|
||||
[], "", ST_tc_st_SLOT01>, AddrModeRel {
|
||||
|
|
@ -3512,7 +3512,7 @@ class T_StoreAbs_Pred <string mnemonic, RegisterClass RC, bits<2> MajOp,
|
|||
//===----------------------------------------------------------------------===//
|
||||
class T_StoreAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
|
||||
bits<2> MajOp, bit isHalf>
|
||||
: T_StoreAbsGP <mnemonic, RC, u32MustExt, MajOp, 1, isHalf>,
|
||||
: T_StoreAbsGP <mnemonic, RC, u32_0MustExt, MajOp, 1, isHalf>,
|
||||
AddrModeRel {
|
||||
string ImmOpStr = !cast<string>(ImmOp);
|
||||
let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
|
||||
|
|
@ -3584,7 +3584,7 @@ class T_StoreAbsGP_NV <string mnemonic, Operand ImmOp, bits<2>MajOp>
|
|||
let hasSideEffects = 0, isPredicated = 1, mayStore = 1, isNVStore = 1,
|
||||
isNewValue = 1, opNewValue = 2, opExtentBits = 6, opExtendable = 1 in
|
||||
class T_StoreAbs_NV_Pred <string mnemonic, bits<2> MajOp, bit isNot, bit isNew>
|
||||
: NVInst_V4<(outs), (ins PredRegs:$src1, u32MustExt:$absaddr, IntRegs:$src2),
|
||||
: NVInst_V4<(outs), (ins PredRegs:$src1, u32_0MustExt:$absaddr, IntRegs:$src2),
|
||||
!if(isNot, "if (!$src1", "if ($src1")#!if(isNew, ".new) ",
|
||||
") ")#mnemonic#"(#$absaddr) = $src2.new",
|
||||
[], "", ST_tc_st_SLOT0>, AddrModeRel {
|
||||
|
|
@ -3614,7 +3614,7 @@ class T_StoreAbs_NV_Pred <string mnemonic, bits<2> MajOp, bit isNot, bit isNew>
|
|||
// absolute addressing.
|
||||
//===----------------------------------------------------------------------===//
|
||||
class T_StoreAbs_NV <string mnemonic, Operand ImmOp, bits<2> MajOp>
|
||||
: T_StoreAbsGP_NV <mnemonic, u32MustExt, MajOp>, AddrModeRel {
|
||||
: T_StoreAbsGP_NV <mnemonic, u32_0MustExt, MajOp>, AddrModeRel {
|
||||
|
||||
string ImmOpStr = !cast<string>(ImmOp);
|
||||
let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
|
||||
|
|
@ -3794,7 +3794,7 @@ class T_LoadAbsGP <string mnemonic, RegisterClass RC, Operand ImmOp,
|
|||
|
||||
class T_LoadAbs <string mnemonic, RegisterClass RC, Operand ImmOp,
|
||||
bits<3> MajOp>
|
||||
: T_LoadAbsGP <mnemonic, RC, u32MustExt, MajOp>, AddrModeRel {
|
||||
: T_LoadAbsGP <mnemonic, RC, u32_0MustExt, MajOp>, AddrModeRel {
|
||||
|
||||
string ImmOpStr = !cast<string>(ImmOp);
|
||||
let opExtentBits = !if (!eq(ImmOpStr, "u16_3Imm"), 19,
|
||||
|
|
@ -3816,7 +3816,7 @@ let isPredicated = 1, hasSideEffects = 0, hasNewValue = 1, opExtentBits = 6,
|
|||
opExtendable = 2 in
|
||||
class T_LoadAbs_Pred <string mnemonic, RegisterClass RC, bits<3> MajOp,
|
||||
bit isPredNot, bit isPredNew>
|
||||
: LDInst <(outs RC:$dst), (ins PredRegs:$src1, u32MustExt:$absaddr),
|
||||
: LDInst <(outs RC:$dst), (ins PredRegs:$src1, u32_0MustExt:$absaddr),
|
||||
!if(isPredNot, "if (!$src1", "if ($src1")#!if(isPredNew, ".new) ",
|
||||
") ")#"$dst = "#mnemonic#"(#$absaddr)">, AddrModeRel {
|
||||
bits<5> dst;
|
||||
|
|
@ -3967,22 +3967,22 @@ let AddedComplexity = 100 in {
|
|||
}
|
||||
|
||||
// Transfer global address into a register
|
||||
def: Pat<(HexagonCONST32 tglobaladdr:$Rs), (A2_tfrsi s16Ext:$Rs)>;
|
||||
def: Pat<(HexagonCONST32_GP tblockaddress:$Rs), (A2_tfrsi s16Ext:$Rs)>;
|
||||
def: Pat<(HexagonCONST32_GP tglobaladdr:$Rs), (A2_tfrsi s16Ext:$Rs)>;
|
||||
def: Pat<(HexagonCONST32 tglobaladdr:$Rs), (A2_tfrsi s16_0Ext:$Rs)>;
|
||||
def: Pat<(HexagonCONST32_GP tblockaddress:$Rs), (A2_tfrsi s16_0Ext:$Rs)>;
|
||||
def: Pat<(HexagonCONST32_GP tglobaladdr:$Rs), (A2_tfrsi s16_0Ext:$Rs)>;
|
||||
|
||||
let AddedComplexity = 30 in {
|
||||
def: Storea_pat<truncstorei8, I32, u32ImmPred, PS_storerbabs>;
|
||||
def: Storea_pat<truncstorei16, I32, u32ImmPred, PS_storerhabs>;
|
||||
def: Storea_pat<store, I32, u32ImmPred, PS_storeriabs>;
|
||||
def: Storea_pat<truncstorei8, I32, u32_0ImmPred, PS_storerbabs>;
|
||||
def: Storea_pat<truncstorei16, I32, u32_0ImmPred, PS_storerhabs>;
|
||||
def: Storea_pat<store, I32, u32_0ImmPred, PS_storeriabs>;
|
||||
}
|
||||
|
||||
let AddedComplexity = 30 in {
|
||||
def: Loada_pat<load, i32, u32ImmPred, PS_loadriabs>;
|
||||
def: Loada_pat<sextloadi8, i32, u32ImmPred, PS_loadrbabs>;
|
||||
def: Loada_pat<zextloadi8, i32, u32ImmPred, PS_loadrubabs>;
|
||||
def: Loada_pat<sextloadi16, i32, u32ImmPred, PS_loadrhabs>;
|
||||
def: Loada_pat<zextloadi16, i32, u32ImmPred, PS_loadruhabs>;
|
||||
def: Loada_pat<load, i32, u32_0ImmPred, PS_loadriabs>;
|
||||
def: Loada_pat<sextloadi8, i32, u32_0ImmPred, PS_loadrbabs>;
|
||||
def: Loada_pat<zextloadi8, i32, u32_0ImmPred, PS_loadrubabs>;
|
||||
def: Loada_pat<sextloadi16, i32, u32_0ImmPred, PS_loadrhabs>;
|
||||
def: Loada_pat<zextloadi16, i32, u32_0ImmPred, PS_loadruhabs>;
|
||||
}
|
||||
|
||||
// Indexed store word - global address.
|
||||
|
|
@ -4278,7 +4278,7 @@ let isBranch = 1, hasSideEffects = 0, isExtentSigned = 1,
|
|||
isPredicated = 1, isPredicatedNew = 1, isExtendable = 1, opExtentBits = 11,
|
||||
opExtentAlign = 2, opExtendable = 2, isTerminator = 1 in
|
||||
class CJInst_RU5<string px, string op, bit np, string tnt>
|
||||
: InstHexagon<(outs), (ins IntRegs:$Rs, u5Imm:$U5, brtarget:$r9_2),
|
||||
: InstHexagon<(outs), (ins IntRegs:$Rs, u5_0Imm:$U5, brtarget:$r9_2),
|
||||
""#px#" = cmp."#op#"($Rs, #$U5); if ("
|
||||
#!if(np, "!","")#""#px#".new) jump:"#tnt#" $r9_2",
|
||||
[], "", COMPOUND_CJ_ARCHDEPSLOT, TypeCOMPOUND>, OpcodeHexagon {
|
||||
|
|
@ -4387,7 +4387,7 @@ let Defs = [PC], isBranch = 1, hasSideEffects = 0, hasNewValue = 1,
|
|||
opExtentAlign = 2, opExtendable = 2 in
|
||||
def J4_jumpseti: CJInst_JMPSET <
|
||||
(outs IntRegs:$Rd),
|
||||
(ins u6Imm:$U6, brtarget:$r9_2),
|
||||
(ins u6_0Imm:$U6, brtarget:$r9_2),
|
||||
"$Rd = #$U6 ; jump $r9_2"> {
|
||||
bits<4> Rd;
|
||||
bits<6> U6;
|
||||
|
|
|
|||
|
|
@ -52,9 +52,9 @@ let Predicates = [HasV5T] in {
|
|||
def A5_vaddhubs: T_S3op_1 <"vaddhub", IntRegs, 0b01, 0b001, 0, 1>;
|
||||
}
|
||||
|
||||
def S2_asr_i_p_rnd : S_2OpInstImm<"asr", 0b110, 0b111, u6Imm,
|
||||
def S2_asr_i_p_rnd : S_2OpInstImm<"asr", 0b110, 0b111, u6_0Imm,
|
||||
[(set I64:$dst,
|
||||
(sra (i64 (add (i64 (sra I64:$src1, u6ImmPred:$src2)), 1)),
|
||||
(sra (i64 (add (i64 (sra I64:$src1, u6_0ImmPred:$src2)), 1)),
|
||||
(i32 1)))], 1>,
|
||||
Requires<[HasV5T]> {
|
||||
bits<6> src2;
|
||||
|
|
@ -63,7 +63,7 @@ def S2_asr_i_p_rnd : S_2OpInstImm<"asr", 0b110, 0b111, u6Imm,
|
|||
|
||||
let isAsmParserOnly = 1 in
|
||||
def S2_asr_i_p_rnd_goodsyntax
|
||||
: MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
|
||||
: MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6_0Imm:$src2),
|
||||
"$dst = asrrnd($src1, #$src2)">;
|
||||
|
||||
def C4_fastcorner9 : T_LOGICAL_2OP<"fastcorner9", 0b000, 0, 0>,
|
||||
|
|
@ -118,7 +118,7 @@ let AddedComplexity = 20 in {
|
|||
}
|
||||
|
||||
let AddedComplexity = 80 in {
|
||||
def: Loada_pat<load, f32, u32ImmPred, PS_loadriabs>;
|
||||
def: Loada_pat<load, f32, u32_0ImmPred, PS_loadriabs>;
|
||||
def: Loada_pat<load, f32, addrga, PS_loadriabs>;
|
||||
def: Loada_pat<load, f64, addrga, PS_loadrdabs>;
|
||||
}
|
||||
|
|
@ -828,7 +828,7 @@ def: Pat<(i32 (fp_to_sint F64:$src1)),
|
|||
let Defs = [USR_OVF], hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
|
||||
class T_ASRHUB<bit isSat>
|
||||
: SInst <(outs IntRegs:$Rd),
|
||||
(ins DoubleRegs:$Rss, u4Imm:$u4),
|
||||
(ins DoubleRegs:$Rss, u4_0Imm:$u4),
|
||||
"$Rd = vasrhub($Rss, #$u4):"#!if(isSat, "sat", "raw"),
|
||||
[], "", S_2op_tc_2_SLOT23>,
|
||||
Requires<[HasV5T]> {
|
||||
|
|
@ -852,13 +852,13 @@ def S5_asrhub_sat : T_ASRHUB <1>;
|
|||
|
||||
let isAsmParserOnly = 1 in
|
||||
def S5_asrhub_rnd_sat_goodsyntax
|
||||
: SInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, u4Imm:$u4),
|
||||
: SInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, u4_0Imm:$u4),
|
||||
"$Rd = vasrhub($Rss, #$u4):rnd:sat">, Requires<[HasV5T]>;
|
||||
|
||||
// S5_vasrhrnd: Vector arithmetic shift right by immediate with round.
|
||||
let hasSideEffects = 0 in
|
||||
def S5_vasrhrnd : SInst <(outs DoubleRegs:$Rdd),
|
||||
(ins DoubleRegs:$Rss, u4Imm:$u4),
|
||||
(ins DoubleRegs:$Rss, u4_0Imm:$u4),
|
||||
"$Rdd = vasrh($Rss, #$u4):raw">,
|
||||
Requires<[HasV5T]> {
|
||||
bits<5> Rdd;
|
||||
|
|
@ -877,7 +877,7 @@ def S5_vasrhrnd : SInst <(outs DoubleRegs:$Rdd),
|
|||
|
||||
let isAsmParserOnly = 1 in
|
||||
def S5_vasrhrnd_goodsyntax
|
||||
: SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, u4Imm:$u4),
|
||||
: SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, u4_0Imm:$u4),
|
||||
"$Rdd = vasrh($Rss,#$u4):rnd">, Requires<[HasV5T]>;
|
||||
|
||||
// Floating point reciprocal square root approximation
|
||||
|
|
@ -913,7 +913,7 @@ let Uses = [USR], isFP = 1 in
|
|||
def F2_sfclass : T_TEST_BIT_IMM<"sfclass", 0b111>;
|
||||
|
||||
let Uses = [USR], isFP = 1 in
|
||||
def F2_dfclass: ALU64Inst<(outs PredRegs:$Pd), (ins DoubleRegs:$Rss, u5Imm:$u5),
|
||||
def F2_dfclass: ALU64Inst<(outs PredRegs:$Pd), (ins DoubleRegs:$Rss, u5_0Imm:$u5),
|
||||
"$Pd = dfclass($Rss, #$u5)",
|
||||
[], "" , ALU64_tc_2early_SLOT23 > , Requires<[HasV5T]> {
|
||||
bits<2> Pd;
|
||||
|
|
@ -931,7 +931,7 @@ def F2_dfclass: ALU64Inst<(outs PredRegs:$Pd), (ins DoubleRegs:$Rss, u5Imm:$u5),
|
|||
|
||||
// Instructions to create floating point constant
|
||||
class T_fimm <string mnemonic, RegisterClass RC, bits<4> RegType, bit isNeg>
|
||||
: ALU64Inst<(outs RC:$dst), (ins u10Imm:$src),
|
||||
: ALU64Inst<(outs RC:$dst), (ins u10_0Imm:$src),
|
||||
"$dst = "#mnemonic#"(#$src)"#!if(isNeg, ":neg", ":pos"),
|
||||
[], "", ALU64_tc_2_SLOT23>, Requires<[HasV5T]> {
|
||||
bits<5> dst;
|
||||
|
|
|
|||
|
|
@ -862,7 +862,7 @@ defm : vL32b_ai_pats <v8i64, v16i64>;
|
|||
|
||||
let isPseudo = 1, isCodeGenOnly = 1, validSubTargets = HasV60SubT in
|
||||
class STrivv_template<RegisterClass RC>
|
||||
: V6_STInst<(outs), (ins IntRegs:$addr, s32Imm:$off, RC:$src), "", []>;
|
||||
: V6_STInst<(outs), (ins IntRegs:$addr, s32_0Imm:$off, RC:$src), "", []>;
|
||||
|
||||
def PS_vstorerw_ai: STrivv_template<VecDblRegs>,
|
||||
Requires<[HasV60T,UseHVXSgl]>;
|
||||
|
|
@ -899,7 +899,7 @@ defm : STrivv_pats <v16i64, v32i64>;
|
|||
|
||||
let isPseudo = 1, isCodeGenOnly = 1, validSubTargets = HasV60SubT in
|
||||
class LDrivv_template<RegisterClass RC>
|
||||
: V6_LDInst<(outs RC:$dst), (ins IntRegs:$addr, s32Imm:$off), "", []>;
|
||||
: V6_LDInst<(outs RC:$dst), (ins IntRegs:$addr, s32_0Imm:$off), "", []>;
|
||||
|
||||
def PS_vloadrw_ai: LDrivv_template<VecDblRegs>,
|
||||
Requires<[HasV60T,UseHVXSgl]>;
|
||||
|
|
@ -935,11 +935,11 @@ defm : LDrivv_pats <v16i64, v32i64>;
|
|||
let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
|
||||
isCodeGenOnly = 1, isPseudo = 1, mayStore = 1, hasSideEffects = 0 in {
|
||||
def PS_vstorerq_ai : STInst<(outs),
|
||||
(ins IntRegs:$base, s32Imm:$offset, VecPredRegs:$src1),
|
||||
(ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs:$src1),
|
||||
".error \"should not emit\"", []>,
|
||||
Requires<[HasV60T,UseHVXSgl]>;
|
||||
def PS_vstorerq_ai_128B : STInst<(outs),
|
||||
(ins IntRegs:$base, s32Imm:$offset, VecPredRegs128B:$src1),
|
||||
(ins IntRegs:$base, s32_0Imm:$offset, VecPredRegs128B:$src1),
|
||||
".error \"should not emit\"", []>,
|
||||
Requires<[HasV60T,UseHVXDbl]>;
|
||||
}
|
||||
|
|
@ -948,11 +948,11 @@ let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
|
|||
let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
|
||||
opExtentAlign = 2, isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in {
|
||||
def PS_vloadrq_ai : LDInst<(outs VecPredRegs:$dst),
|
||||
(ins IntRegs:$base, s32Imm:$offset),
|
||||
(ins IntRegs:$base, s32_0Imm:$offset),
|
||||
".error \"should not emit\"", []>,
|
||||
Requires<[HasV60T,UseHVXSgl]>;
|
||||
def PS_vloadrq_ai_128B : LDInst<(outs VecPredRegs128B:$dst),
|
||||
(ins IntRegs:$base, s32Imm:$offset),
|
||||
(ins IntRegs:$base, s32_0Imm:$offset),
|
||||
".error \"should not emit\"", []>,
|
||||
Requires<[HasV60T,UseHVXDbl]>;
|
||||
}
|
||||
|
|
@ -1760,7 +1760,7 @@ let isAccumulator = 1, hasNewValue = 1, Itinerary = CVI_VX_DV_LONG,
|
|||
Type = TypeCVI_VX_DV in
|
||||
class T_HVX_vmpyacc2 <string asmString, RegisterClass RC>
|
||||
: CVI_VA_Resource1 <(outs RC:$dst),
|
||||
(ins RC:$_src_, RC:$src1, IntRegs:$src2, u1Imm:$src3),
|
||||
(ins RC:$_src_, RC:$src1, IntRegs:$src2, u1_0Imm:$src3),
|
||||
asmString, [], "$dst = $_src_" > ;
|
||||
|
||||
|
||||
|
|
@ -1784,7 +1784,7 @@ defm V6_vrmpyubi_acc :
|
|||
|
||||
let Itinerary = CVI_VX_DV_LONG, Type = TypeCVI_VX_DV, hasNewValue = 1 in
|
||||
class T_HVX_vmpy2 <string asmString, RegisterClass RC>
|
||||
: CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1, IntRegs:$src2, u1Imm:$src3),
|
||||
: CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1, IntRegs:$src2, u1_0Imm:$src3),
|
||||
asmString>;
|
||||
|
||||
|
||||
|
|
@ -1936,7 +1936,7 @@ defm V6_vunpackoh : T_HVX_unpack <"$dst.w |= vunpacko($src1.h)">, V6_vunpackoh_e
|
|||
let Itinerary = CVI_VP_LONG, Type = TypeCVI_VP, hasNewValue = 1,
|
||||
hasSideEffects = 0 in
|
||||
class T_HVX_valign <string asmString, RegisterClass RC>
|
||||
: CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1, RC:$src2, u3Imm:$src3),
|
||||
: CVI_VA_Resource1<(outs RC:$dst), (ins RC:$src1, RC:$src2, u3_0Imm:$src3),
|
||||
asmString>;
|
||||
|
||||
multiclass T_HVX_valign <string asmString> {
|
||||
|
|
@ -2073,9 +2073,9 @@ class T_HVX_rol <string asmString, RegisterClass RC, Operand ImmOp >
|
|||
: SInst2 <(outs RC:$dst), (ins RC:$src1, ImmOp:$src2), asmString>;
|
||||
|
||||
class T_HVX_rol_R <string asmString>
|
||||
: T_HVX_rol <asmString, IntRegs, u5Imm>;
|
||||
: T_HVX_rol <asmString, IntRegs, u5_0Imm>;
|
||||
class T_HVX_rol_P <string asmString>
|
||||
: T_HVX_rol <asmString, DoubleRegs, u6Imm>;
|
||||
: T_HVX_rol <asmString, DoubleRegs, u6_0Imm>;
|
||||
|
||||
def S6_rol_i_p : T_HVX_rol_P <"$dst = rol($src1,#$src2)">, S6_rol_i_p_enc;
|
||||
let hasNewValue = 1, opNewValue = 0 in
|
||||
|
|
@ -2087,10 +2087,10 @@ class T_HVX_rol_acc <string asmString, RegisterClass RC, Operand ImmOp>
|
|||
asmString, [], "$dst = $_src_" >;
|
||||
|
||||
class T_HVX_rol_acc_P <string asmString>
|
||||
: T_HVX_rol_acc <asmString, DoubleRegs, u6Imm>;
|
||||
: T_HVX_rol_acc <asmString, DoubleRegs, u6_0Imm>;
|
||||
|
||||
class T_HVX_rol_acc_R <string asmString>
|
||||
: T_HVX_rol_acc <asmString, IntRegs, u5Imm>;
|
||||
: T_HVX_rol_acc <asmString, IntRegs, u5_0Imm>;
|
||||
|
||||
def S6_rol_i_p_nac :
|
||||
T_HVX_rol_acc_P <"$dst -= rol($src1,#$src2)">, S6_rol_i_p_nac_enc;
|
||||
|
|
|
|||
|
|
@ -51,17 +51,17 @@ defm : bitconvert_64<v2i32, i64>;
|
|||
// As a result, special care is needed to guarantee correctness and
|
||||
// performance.
|
||||
class vshift_v4i16<SDNode Op, string Str, bits<3>MajOp, bits<3>MinOp>
|
||||
: S_2OpInstImm<Str, MajOp, MinOp, u4Imm,
|
||||
: S_2OpInstImm<Str, MajOp, MinOp, u4_0Imm,
|
||||
[(set (v4i16 DoubleRegs:$dst),
|
||||
(Op (v4i16 DoubleRegs:$src1), u4ImmPred:$src2))]> {
|
||||
(Op (v4i16 DoubleRegs:$src1), u4_0ImmPred:$src2))]> {
|
||||
bits<4> src2;
|
||||
let Inst{11-8} = src2;
|
||||
}
|
||||
|
||||
class vshift_v2i32<SDNode Op, string Str, bits<3>MajOp, bits<3>MinOp>
|
||||
: S_2OpInstImm<Str, MajOp, MinOp, u5Imm,
|
||||
: S_2OpInstImm<Str, MajOp, MinOp, u5_0Imm,
|
||||
[(set (v2i32 DoubleRegs:$dst),
|
||||
(Op (v2i32 DoubleRegs:$src1), u5ImmPred:$src2))]> {
|
||||
(Op (v2i32 DoubleRegs:$src1), u5_0ImmPred:$src2))]> {
|
||||
bits<5> src2;
|
||||
let Inst{12-8} = src2;
|
||||
}
|
||||
|
|
@ -118,21 +118,21 @@ def: VArith_pat <A2_xorp, xor, V8I8>;
|
|||
def: VArith_pat <A2_xorp, xor, V4I16>;
|
||||
def: VArith_pat <A2_xorp, xor, V2I32>;
|
||||
|
||||
def: Pat<(v2i32 (sra V2I32:$b, (i64 (HexagonCOMBINE (i32 u5ImmPred:$c),
|
||||
(i32 u5ImmPred:$c))))),
|
||||
def: Pat<(v2i32 (sra V2I32:$b, (i64 (HexagonCOMBINE (i32 u5_0ImmPred:$c),
|
||||
(i32 u5_0ImmPred:$c))))),
|
||||
(S2_asr_i_vw V2I32:$b, imm:$c)>;
|
||||
def: Pat<(v2i32 (srl V2I32:$b, (i64 (HexagonCOMBINE (i32 u5ImmPred:$c),
|
||||
(i32 u5ImmPred:$c))))),
|
||||
def: Pat<(v2i32 (srl V2I32:$b, (i64 (HexagonCOMBINE (i32 u5_0ImmPred:$c),
|
||||
(i32 u5_0ImmPred:$c))))),
|
||||
(S2_lsr_i_vw V2I32:$b, imm:$c)>;
|
||||
def: Pat<(v2i32 (shl V2I32:$b, (i64 (HexagonCOMBINE (i32 u5ImmPred:$c),
|
||||
(i32 u5ImmPred:$c))))),
|
||||
def: Pat<(v2i32 (shl V2I32:$b, (i64 (HexagonCOMBINE (i32 u5_0ImmPred:$c),
|
||||
(i32 u5_0ImmPred:$c))))),
|
||||
(S2_asl_i_vw V2I32:$b, imm:$c)>;
|
||||
|
||||
def: Pat<(v4i16 (sra V4I16:$b, (v4i16 (HexagonVSPLATH (i32 (u4ImmPred:$c)))))),
|
||||
def: Pat<(v4i16 (sra V4I16:$b, (v4i16 (HexagonVSPLATH (i32 (u4_0ImmPred:$c)))))),
|
||||
(S2_asr_i_vh V4I16:$b, imm:$c)>;
|
||||
def: Pat<(v4i16 (srl V4I16:$b, (v4i16 (HexagonVSPLATH (i32 (u4ImmPred:$c)))))),
|
||||
def: Pat<(v4i16 (srl V4I16:$b, (v4i16 (HexagonVSPLATH (i32 (u4_0ImmPred:$c)))))),
|
||||
(S2_lsr_i_vh V4I16:$b, imm:$c)>;
|
||||
def: Pat<(v4i16 (shl V4I16:$b, (v4i16 (HexagonVSPLATH (i32 (u4ImmPred:$c)))))),
|
||||
def: Pat<(v4i16 (shl V4I16:$b, (v4i16 (HexagonVSPLATH (i32 (u4_0ImmPred:$c)))))),
|
||||
(S2_asl_i_vh V4I16:$b, imm:$c)>;
|
||||
|
||||
|
||||
|
|
@ -148,17 +148,17 @@ def HexagonVSRLH: SDNode<"HexagonISD::VSRLH", SDTHexagon_v4i16_v4i16_i32>;
|
|||
def HexagonVSHLW: SDNode<"HexagonISD::VSHLW", SDTHexagon_v2i32_v2i32_i32>;
|
||||
def HexagonVSHLH: SDNode<"HexagonISD::VSHLH", SDTHexagon_v4i16_v4i16_i32>;
|
||||
|
||||
def: Pat<(v2i32 (HexagonVSRAW V2I32:$Rs, u5ImmPred:$u5)),
|
||||
def: Pat<(v2i32 (HexagonVSRAW V2I32:$Rs, u5_0ImmPred:$u5)),
|
||||
(S2_asr_i_vw V2I32:$Rs, imm:$u5)>;
|
||||
def: Pat<(v4i16 (HexagonVSRAH V4I16:$Rs, u4ImmPred:$u4)),
|
||||
def: Pat<(v4i16 (HexagonVSRAH V4I16:$Rs, u4_0ImmPred:$u4)),
|
||||
(S2_asr_i_vh V4I16:$Rs, imm:$u4)>;
|
||||
def: Pat<(v2i32 (HexagonVSRLW V2I32:$Rs, u5ImmPred:$u5)),
|
||||
def: Pat<(v2i32 (HexagonVSRLW V2I32:$Rs, u5_0ImmPred:$u5)),
|
||||
(S2_lsr_i_vw V2I32:$Rs, imm:$u5)>;
|
||||
def: Pat<(v4i16 (HexagonVSRLH V4I16:$Rs, u4ImmPred:$u4)),
|
||||
def: Pat<(v4i16 (HexagonVSRLH V4I16:$Rs, u4_0ImmPred:$u4)),
|
||||
(S2_lsr_i_vh V4I16:$Rs, imm:$u4)>;
|
||||
def: Pat<(v2i32 (HexagonVSHLW V2I32:$Rs, u5ImmPred:$u5)),
|
||||
def: Pat<(v2i32 (HexagonVSHLW V2I32:$Rs, u5_0ImmPred:$u5)),
|
||||
(S2_asl_i_vw V2I32:$Rs, imm:$u5)>;
|
||||
def: Pat<(v4i16 (HexagonVSHLH V4I16:$Rs, u4ImmPred:$u4)),
|
||||
def: Pat<(v4i16 (HexagonVSHLH V4I16:$Rs, u4_0ImmPred:$u4)),
|
||||
(S2_asl_i_vh V4I16:$Rs, imm:$u4)>;
|
||||
|
||||
// Vector shift words by register
|
||||
|
|
|
|||
|
|
@ -774,13 +774,13 @@ def: T_RR_pat<A2_combine_hl, int_hexagon_A2_combine_hl>;
|
|||
def: T_RR_pat<A2_combine_lh, int_hexagon_A2_combine_lh>;
|
||||
def: T_RR_pat<A2_combine_ll, int_hexagon_A2_combine_ll>;
|
||||
|
||||
def: T_II_pat<A2_combineii, int_hexagon_A2_combineii, s32ImmPred, s8ImmPred>;
|
||||
def: T_II_pat<A2_combineii, int_hexagon_A2_combineii, s32_0ImmPred, s8_0ImmPred>;
|
||||
|
||||
// Mux
|
||||
def : T_QRR_pat<C2_mux, int_hexagon_C2_mux>;
|
||||
def : T_QRI_pat<C2_muxir, int_hexagon_C2_muxir, s32ImmPred>;
|
||||
def : T_QIR_pat<C2_muxri, int_hexagon_C2_muxri, s32ImmPred>;
|
||||
def : T_QII_pat<C2_muxii, int_hexagon_C2_muxii, s32ImmPred, s8ImmPred>;
|
||||
def : T_QRI_pat<C2_muxir, int_hexagon_C2_muxir, s32_0ImmPred>;
|
||||
def : T_QIR_pat<C2_muxri, int_hexagon_C2_muxri, s32_0ImmPred>;
|
||||
def : T_QII_pat<C2_muxii, int_hexagon_C2_muxii, s32_0ImmPred, s8_0ImmPred>;
|
||||
|
||||
// Shift halfword
|
||||
def : T_R_pat<A2_aslh, int_hexagon_A2_aslh>;
|
||||
|
|
@ -801,17 +801,17 @@ def : T_Q_RR_pat<C2_cmpeq, int_hexagon_C2_cmpeq>;
|
|||
def : T_Q_RR_pat<C2_cmpgt, int_hexagon_C2_cmpgt>;
|
||||
def : T_Q_RR_pat<C2_cmpgtu, int_hexagon_C2_cmpgtu>;
|
||||
|
||||
def : T_Q_RI_pat<C2_cmpeqi, int_hexagon_C2_cmpeqi, s32ImmPred>;
|
||||
def : T_Q_RI_pat<C2_cmpgti, int_hexagon_C2_cmpgti, s32ImmPred>;
|
||||
def : T_Q_RI_pat<C2_cmpgtui, int_hexagon_C2_cmpgtui, u32ImmPred>;
|
||||
def : T_Q_RI_pat<C2_cmpeqi, int_hexagon_C2_cmpeqi, s32_0ImmPred>;
|
||||
def : T_Q_RI_pat<C2_cmpgti, int_hexagon_C2_cmpgti, s32_0ImmPred>;
|
||||
def : T_Q_RI_pat<C2_cmpgtui, int_hexagon_C2_cmpgtui, u32_0ImmPred>;
|
||||
|
||||
def : Pat <(int_hexagon_C2_cmpgei I32:$src1, s32ImmPred:$src2),
|
||||
def : Pat <(int_hexagon_C2_cmpgei I32:$src1, s32_0ImmPred:$src2),
|
||||
(C2_tfrpr (C2_cmpgti I32:$src1,
|
||||
(DEC_CONST_SIGNED s32ImmPred:$src2)))>;
|
||||
(DEC_CONST_SIGNED s32_0ImmPred:$src2)))>;
|
||||
|
||||
def : Pat <(int_hexagon_C2_cmpgeui I32:$src1, u32ImmPred:$src2),
|
||||
def : Pat <(int_hexagon_C2_cmpgeui I32:$src1, u32_0ImmPred:$src2),
|
||||
(C2_tfrpr (C2_cmpgtui I32:$src1,
|
||||
(DEC_CONST_UNSIGNED u32ImmPred:$src2)))>;
|
||||
(DEC_CONST_UNSIGNED u32_0ImmPred:$src2)))>;
|
||||
|
||||
def : Pat <(int_hexagon_C2_cmpgeui I32:$src, 0),
|
||||
(C2_tfrpr (C2_cmpeq I32:$src, I32:$src))>;
|
||||
|
|
@ -1104,14 +1104,14 @@ def : Pat<(i64 (int_hexagon_S2_insertp_rp I64:$src1, I64:$src2, I64:$src3)),
|
|||
(i64 (S2_insertp_rp I64:$src1, I64:$src2, I64:$src3))>;
|
||||
|
||||
def : Pat<(int_hexagon_S2_insert I32:$src1, I32:$src2,
|
||||
u5ImmPred:$src3, u5ImmPred:$src4),
|
||||
u5_0ImmPred:$src3, u5_0ImmPred:$src4),
|
||||
(S2_insert I32:$src1, I32:$src2,
|
||||
u5ImmPred:$src3, u5ImmPred:$src4)>;
|
||||
u5_0ImmPred:$src3, u5_0ImmPred:$src4)>;
|
||||
|
||||
def : Pat<(i64 (int_hexagon_S2_insertp I64:$src1, I64:$src2,
|
||||
u6ImmPred:$src3, u6ImmPred:$src4)),
|
||||
u6_0ImmPred:$src3, u6_0ImmPred:$src4)),
|
||||
(i64 (S2_insertp I64:$src1, I64:$src2,
|
||||
u6ImmPred:$src3, u6ImmPred:$src4))>;
|
||||
u6_0ImmPred:$src3, u6_0ImmPred:$src4))>;
|
||||
|
||||
// Innterleave/deinterleave
|
||||
def : T_P_pat <S2_interleave, int_hexagon_S2_interleave>;
|
||||
|
|
@ -1239,9 +1239,9 @@ def : T_RI_pat <S2_asl_i_r_sat, int_hexagon_S2_asl_i_r_sat>;
|
|||
//===----------------------------------------------------------------------===//
|
||||
class S2op_tableidx_pat <Intrinsic IntID, InstHexagon OutputInst,
|
||||
SDNodeXForm XformImm>
|
||||
: Pat <(IntID I32:$src1, I32:$src2, u4ImmPred:$src3, u5ImmPred:$src4),
|
||||
(OutputInst I32:$src1, I32:$src2, u4ImmPred:$src3,
|
||||
(XformImm u5ImmPred:$src4))>;
|
||||
: Pat <(IntID I32:$src1, I32:$src2, u4_0ImmPred:$src3, u5_0ImmPred:$src4),
|
||||
(OutputInst I32:$src1, I32:$src2, u4_0ImmPred:$src3,
|
||||
(XformImm u5_0ImmPred:$src4))>;
|
||||
|
||||
|
||||
// Table Index : Extract and insert bits.
|
||||
|
|
@ -1250,9 +1250,9 @@ class S2op_tableidx_pat <Intrinsic IntID, InstHexagon OutputInst,
|
|||
// needed for int_hexagon_S2_tableidxb_goodsyntax.
|
||||
|
||||
def : Pat <(int_hexagon_S2_tableidxb_goodsyntax I32:$src1, I32:$src2,
|
||||
u4ImmPred:$src3, u5ImmPred:$src4),
|
||||
u4_0ImmPred:$src3, u5_0ImmPred:$src4),
|
||||
(S2_tableidxb I32:$src1, I32:$src2,
|
||||
u4ImmPred:$src3, u5ImmPred:$src4)>;
|
||||
u4_0ImmPred:$src3, u5_0ImmPred:$src4)>;
|
||||
|
||||
def : S2op_tableidx_pat <int_hexagon_S2_tableidxh_goodsyntax, S2_tableidxh,
|
||||
DEC_CONST_SIGNED>;
|
||||
|
|
|
|||
|
|
@ -167,15 +167,15 @@ def : T_PPR_pat <A4_vrminuw, int_hexagon_A4_vrminuw>;
|
|||
|
||||
// Rotate and reduce bytes
|
||||
def : Pat <(int_hexagon_S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2,
|
||||
u2ImmPred:$src3),
|
||||
(S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2ImmPred:$src3)>;
|
||||
u2_0ImmPred:$src3),
|
||||
(S4_vrcrotate DoubleRegs:$src1, IntRegs:$src2, u2_0ImmPred:$src3)>;
|
||||
|
||||
// Rotate and reduce bytes with accumulation
|
||||
// Rxx+=vrcrotate(Rss,Rt,#u2)
|
||||
def : Pat <(int_hexagon_S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2,
|
||||
IntRegs:$src3, u2ImmPred:$src4),
|
||||
IntRegs:$src3, u2_0ImmPred:$src4),
|
||||
(S4_vrcrotate_acc DoubleRegs:$src1, DoubleRegs:$src2,
|
||||
IntRegs:$src3, u2ImmPred:$src4)>;
|
||||
IntRegs:$src3, u2_0ImmPred:$src4)>;
|
||||
|
||||
// Vector conditional negate
|
||||
def : T_PPR_pat<S2_vrcnegh, int_hexagon_S2_vrcnegh>;
|
||||
|
|
@ -223,17 +223,17 @@ def: T_RR_pat<A4_orn, int_hexagon_A4_orn>;
|
|||
//*******************************************************************
|
||||
|
||||
// Combine Words Into Doublewords.
|
||||
def: T_RI_pat<A4_combineri, int_hexagon_A4_combineri, s32ImmPred>;
|
||||
def: T_IR_pat<A4_combineir, int_hexagon_A4_combineir, s32ImmPred>;
|
||||
def: T_RI_pat<A4_combineri, int_hexagon_A4_combineri, s32_0ImmPred>;
|
||||
def: T_IR_pat<A4_combineir, int_hexagon_A4_combineir, s32_0ImmPred>;
|
||||
|
||||
//*******************************************************************
|
||||
// ALU32/PRED
|
||||
//*******************************************************************
|
||||
|
||||
// Compare
|
||||
def : T_Q_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi, s32ImmPred>;
|
||||
def : T_Q_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei, s32ImmPred>;
|
||||
def : T_Q_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui, u32ImmPred>;
|
||||
def : T_Q_RI_pat<C4_cmpneqi, int_hexagon_C4_cmpneqi, s32_0ImmPred>;
|
||||
def : T_Q_RI_pat<C4_cmpltei, int_hexagon_C4_cmpltei, s32_0ImmPred>;
|
||||
def : T_Q_RI_pat<C4_cmplteui, int_hexagon_C4_cmplteui, u32_0ImmPred>;
|
||||
|
||||
// Compare To General Register.
|
||||
def: T_Q_RR_pat<C4_cmpneq, int_hexagon_C4_cmpneq>;
|
||||
|
|
|
|||
|
|
@ -15,7 +15,7 @@
|
|||
let isCodeGenOnly = 1, hasSideEffects = 0 in
|
||||
def SA1_combine1i: SUBInst <
|
||||
(outs DoubleRegs:$Rdd),
|
||||
(ins u2Imm:$u2),
|
||||
(ins u2_0Imm:$u2),
|
||||
"$Rdd = combine(#1, #$u2)"> {
|
||||
bits<3> Rdd;
|
||||
bits<2> u2;
|
||||
|
|
@ -63,7 +63,7 @@ def SL2_return_f: SUBInst <
|
|||
let isCodeGenOnly = 1, hasSideEffects = 0 in
|
||||
def SA1_combine3i: SUBInst <
|
||||
(outs DoubleRegs:$Rdd),
|
||||
(ins u2Imm:$u2),
|
||||
(ins u2_0Imm:$u2),
|
||||
"$Rdd = combine(#3, #$u2)"> {
|
||||
bits<3> Rdd;
|
||||
bits<2> u2;
|
||||
|
|
@ -132,7 +132,7 @@ def SL2_jumpr31_tnew: SUBInst <
|
|||
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0, isExtendable = 1, isExtentSigned = 1, opExtentBits = 7, opExtendable = 2 in
|
||||
def SA1_addi: SUBInst <
|
||||
(outs IntRegs:$Rx),
|
||||
(ins IntRegs:$_src_, s7Ext:$s7),
|
||||
(ins IntRegs:$_src_, s7_0Ext:$s7),
|
||||
"$Rx = add($_src_, #$s7)" ,
|
||||
[] ,
|
||||
"$_src_ = $Rx"> {
|
||||
|
|
@ -180,7 +180,7 @@ def SL1_loadri_io: SUBInst <
|
|||
let Defs = [P0], isCodeGenOnly = 1, hasSideEffects = 0 in
|
||||
def SA1_cmpeqi: SUBInst <
|
||||
(outs ),
|
||||
(ins IntRegs:$Rs, u2Imm:$u2),
|
||||
(ins IntRegs:$Rs, u2_0Imm:$u2),
|
||||
"p0 = cmp.eq($Rs, #$u2)"> {
|
||||
bits<4> Rs;
|
||||
bits<2> u2;
|
||||
|
|
@ -362,7 +362,7 @@ def SA1_sxth: SUBInst <
|
|||
let isCodeGenOnly = 1, hasSideEffects = 0 in
|
||||
def SA1_combine0i: SUBInst <
|
||||
(outs DoubleRegs:$Rdd),
|
||||
(ins u2Imm:$u2),
|
||||
(ins u2_0Imm:$u2),
|
||||
"$Rdd = combine(#0, #$u2)"> {
|
||||
bits<3> Rdd;
|
||||
bits<2> u2;
|
||||
|
|
@ -378,7 +378,7 @@ def SA1_combine0i: SUBInst <
|
|||
let isCodeGenOnly = 1, hasSideEffects = 0 in
|
||||
def SA1_combine2i: SUBInst <
|
||||
(outs DoubleRegs:$Rdd),
|
||||
(ins u2Imm:$u2),
|
||||
(ins u2_0Imm:$u2),
|
||||
"$Rdd = combine(#2, #$u2)"> {
|
||||
bits<3> Rdd;
|
||||
bits<2> u2;
|
||||
|
|
@ -584,7 +584,7 @@ def SA1_dec: SUBInst <
|
|||
let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0, isExtendable = 1, isExtentSigned = 0, opExtentBits = 6, opExtendable = 1 in
|
||||
def SA1_seti: SUBInst <
|
||||
(outs IntRegs:$Rd),
|
||||
(ins u6Ext:$u6),
|
||||
(ins u6_0Ext:$u6),
|
||||
"$Rd = #$u6"> {
|
||||
bits<4> Rd;
|
||||
bits<6> u6;
|
||||
|
|
|
|||
|
|
@ -7,58 +7,53 @@
|
|||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
def s32ImmOperand : AsmOperandClass { let Name = "s32Imm"; }
|
||||
def s32_0ImmOperand : AsmOperandClass { let Name = "s32_0Imm"; }
|
||||
def s23_2ImmOperand : AsmOperandClass { let Name = "s23_2Imm"; }
|
||||
def s8ImmOperand : AsmOperandClass { let Name = "s8Imm"; }
|
||||
def s8Imm64Operand : AsmOperandClass { let Name = "s8Imm64"; }
|
||||
def s6ImmOperand : AsmOperandClass { let Name = "s6Imm"; }
|
||||
def s4ImmOperand : AsmOperandClass { let Name = "s4Imm"; }
|
||||
def s8_0ImmOperand : AsmOperandClass { let Name = "s8_0Imm"; }
|
||||
def s8_0Imm64Operand : AsmOperandClass { let Name = "s8_0Imm64"; }
|
||||
def s6_0ImmOperand : AsmOperandClass { let Name = "s6_0Imm"; }
|
||||
def s4_0ImmOperand : AsmOperandClass { let Name = "s4_0Imm"; }
|
||||
def s4_1ImmOperand : AsmOperandClass { let Name = "s4_1Imm"; }
|
||||
def s4_2ImmOperand : AsmOperandClass { let Name = "s4_2Imm"; }
|
||||
def s4_3ImmOperand : AsmOperandClass { let Name = "s4_3Imm"; }
|
||||
def s4_6ImmOperand : AsmOperandClass { let Name = "s4_6Imm"; }
|
||||
def s3_6ImmOperand : AsmOperandClass { let Name = "s3_6Imm"; }
|
||||
def u64ImmOperand : AsmOperandClass { let Name = "u64Imm"; }
|
||||
def u32ImmOperand : AsmOperandClass { let Name = "u32Imm"; }
|
||||
def u64_0ImmOperand : AsmOperandClass { let Name = "u64_0Imm"; }
|
||||
def u32_0ImmOperand : AsmOperandClass { let Name = "u32_0Imm"; }
|
||||
def u26_6ImmOperand : AsmOperandClass { let Name = "u26_6Imm"; }
|
||||
def u16ImmOperand : AsmOperandClass { let Name = "u16Imm"; }
|
||||
def u16_0ImmOperand : AsmOperandClass { let Name = "u16_0Imm"; }
|
||||
def u16_1ImmOperand : AsmOperandClass { let Name = "u16_1Imm"; }
|
||||
def u16_2ImmOperand : AsmOperandClass { let Name = "u16_2Imm"; }
|
||||
def u16_3ImmOperand : AsmOperandClass { let Name = "u16_3Imm"; }
|
||||
def u11_3ImmOperand : AsmOperandClass { let Name = "u11_3Imm"; }
|
||||
def u10ImmOperand : AsmOperandClass { let Name = "u10Imm"; }
|
||||
def u9ImmOperand : AsmOperandClass { let Name = "u9Imm"; }
|
||||
def u8ImmOperand : AsmOperandClass { let Name = "u8Imm"; }
|
||||
def u7ImmOperand : AsmOperandClass { let Name = "u7Imm"; }
|
||||
def u6ImmOperand : AsmOperandClass { let Name = "u6Imm"; }
|
||||
def u10_0ImmOperand : AsmOperandClass { let Name = "u10_0Imm"; }
|
||||
def u9_0ImmOperand : AsmOperandClass { let Name = "u9_0Imm"; }
|
||||
def u8_0ImmOperand : AsmOperandClass { let Name = "u8_0Imm"; }
|
||||
def u7_0ImmOperand : AsmOperandClass { let Name = "u7_0Imm"; }
|
||||
def u6_0ImmOperand : AsmOperandClass { let Name = "u6_0Imm"; }
|
||||
def u6_1ImmOperand : AsmOperandClass { let Name = "u6_1Imm"; }
|
||||
def u6_2ImmOperand : AsmOperandClass { let Name = "u6_2Imm"; }
|
||||
def u6_3ImmOperand : AsmOperandClass { let Name = "u6_3Imm"; }
|
||||
def u5ImmOperand : AsmOperandClass { let Name = "u5Imm"; }
|
||||
def u4ImmOperand : AsmOperandClass { let Name = "u4Imm"; }
|
||||
def u3ImmOperand : AsmOperandClass { let Name = "u3Imm"; }
|
||||
def u2ImmOperand : AsmOperandClass { let Name = "u2Imm"; }
|
||||
def u1ImmOperand : AsmOperandClass { let Name = "u1Imm"; }
|
||||
def n8ImmOperand : AsmOperandClass { let Name = "n8Imm"; }
|
||||
def u5_0ImmOperand : AsmOperandClass { let Name = "u5_0Imm"; }
|
||||
def u4_0ImmOperand : AsmOperandClass { let Name = "u4_0Imm"; }
|
||||
def u3_0ImmOperand : AsmOperandClass { let Name = "u3_0Imm"; }
|
||||
def u2_0ImmOperand : AsmOperandClass { let Name = "u2_0Imm"; }
|
||||
def u1_0ImmOperand : AsmOperandClass { let Name = "u1_0Imm"; }
|
||||
def n8_0ImmOperand : AsmOperandClass { let Name = "n8_0Imm"; }
|
||||
// Immediate operands.
|
||||
|
||||
let OperandType = "OPERAND_IMMEDIATE",
|
||||
DecoderMethod = "unsignedImmDecoder" in {
|
||||
def s32Imm : Operand<i32> { let ParserMatchClass = s32ImmOperand;
|
||||
let DecoderMethod = "s32ImmDecoder"; }
|
||||
def s32_0Imm : Operand<i32> { let ParserMatchClass = s32_0ImmOperand;
|
||||
let DecoderMethod = "s32_0ImmDecoder"; }
|
||||
def s23_2Imm : Operand<i32> { let ParserMatchClass = s23_2ImmOperand; }
|
||||
def s8Imm : Operand<i32> { let ParserMatchClass = s8ImmOperand;
|
||||
let DecoderMethod = "s8ImmDecoder"; }
|
||||
def s8Imm64 : Operand<i64> { let ParserMatchClass = s8Imm64Operand;
|
||||
let DecoderMethod = "s8ImmDecoder"; }
|
||||
def s6Imm : Operand<i32> { let ParserMatchClass = s6ImmOperand;
|
||||
def s8_0Imm : Operand<i32> { let ParserMatchClass = s8_0ImmOperand;
|
||||
let DecoderMethod = "s8_0ImmDecoder"; }
|
||||
def s8_0Imm64 : Operand<i64> { let ParserMatchClass = s8_0Imm64Operand;
|
||||
let DecoderMethod = "s8_0ImmDecoder"; }
|
||||
def s6_0Imm : Operand<i32> { let ParserMatchClass = s6_0ImmOperand;
|
||||
let DecoderMethod = "s6_0ImmDecoder"; }
|
||||
def s6_3Imm : Operand<i32>;
|
||||
def s4Imm : Operand<i32> { let ParserMatchClass = s4ImmOperand;
|
||||
let DecoderMethod = "s4_0ImmDecoder"; }
|
||||
def s4_0Imm : Operand<i32> { let ParserMatchClass = s4_0ImmOperand;
|
||||
let DecoderMethod = "s4_0ImmDecoder"; }
|
||||
def s4_1Imm : Operand<i32> { let ParserMatchClass = s4_1ImmOperand;
|
||||
|
|
@ -67,42 +62,37 @@ let OperandType = "OPERAND_IMMEDIATE",
|
|||
let DecoderMethod = "s4_2ImmDecoder"; }
|
||||
def s4_3Imm : Operand<i32> { let ParserMatchClass = s4_3ImmOperand;
|
||||
let DecoderMethod = "s4_3ImmDecoder"; }
|
||||
def u64Imm : Operand<i64> { let ParserMatchClass = u64ImmOperand; }
|
||||
def u32Imm : Operand<i32> { let ParserMatchClass = u32ImmOperand; }
|
||||
def u64_0Imm : Operand<i64> { let ParserMatchClass = u64_0ImmOperand; }
|
||||
def u32_0Imm : Operand<i32> { let ParserMatchClass = u32_0ImmOperand; }
|
||||
def u26_6Imm : Operand<i32> { let ParserMatchClass = u26_6ImmOperand; }
|
||||
def u16Imm : Operand<i32> { let ParserMatchClass = u16ImmOperand; }
|
||||
def u16_0Imm : Operand<i32> { let ParserMatchClass = u16_0ImmOperand; }
|
||||
def u16_1Imm : Operand<i32> { let ParserMatchClass = u16_1ImmOperand; }
|
||||
def u16_2Imm : Operand<i32> { let ParserMatchClass = u16_2ImmOperand; }
|
||||
def u16_3Imm : Operand<i32> { let ParserMatchClass = u16_3ImmOperand; }
|
||||
def u11_3Imm : Operand<i32> { let ParserMatchClass = u11_3ImmOperand; }
|
||||
def u10Imm : Operand<i32> { let ParserMatchClass = u10ImmOperand; }
|
||||
def u9Imm : Operand<i32> { let ParserMatchClass = u9ImmOperand; }
|
||||
def u8Imm : Operand<i32> { let ParserMatchClass = u8ImmOperand; }
|
||||
def u7Imm : Operand<i32> { let ParserMatchClass = u7ImmOperand; }
|
||||
def u6Imm : Operand<i32> { let ParserMatchClass = u6ImmOperand; }
|
||||
def u10_0Imm : Operand<i32> { let ParserMatchClass = u10_0ImmOperand; }
|
||||
def u9_0Imm : Operand<i32> { let ParserMatchClass = u9_0ImmOperand; }
|
||||
def u8_0Imm : Operand<i32> { let ParserMatchClass = u8_0ImmOperand; }
|
||||
def u7_0Imm : Operand<i32> { let ParserMatchClass = u7_0ImmOperand; }
|
||||
def u6_0Imm : Operand<i32> { let ParserMatchClass = u6_0ImmOperand; }
|
||||
def u6_1Imm : Operand<i32> { let ParserMatchClass = u6_1ImmOperand; }
|
||||
def u6_2Imm : Operand<i32> { let ParserMatchClass = u6_2ImmOperand; }
|
||||
def u6_3Imm : Operand<i32> { let ParserMatchClass = u6_3ImmOperand; }
|
||||
def u5Imm : Operand<i32> { let ParserMatchClass = u5ImmOperand; }
|
||||
def u5_0Imm : Operand<i32>;
|
||||
def u5_0Imm : Operand<i32> { let ParserMatchClass = u5_0ImmOperand; }
|
||||
def u5_1Imm : Operand<i32>;
|
||||
def u5_2Imm : Operand<i32>;
|
||||
def u5_3Imm : Operand<i32>;
|
||||
def u4Imm : Operand<i32> { let ParserMatchClass = u4ImmOperand; }
|
||||
def u4_0Imm : Operand<i32>;
|
||||
def u4_0Imm : Operand<i32> { let ParserMatchClass = u4_0ImmOperand; }
|
||||
def u4_1Imm : Operand<i32>;
|
||||
def u4_2Imm : Operand<i32>;
|
||||
def u4_3Imm : Operand<i32>;
|
||||
def u3Imm : Operand<i32> { let ParserMatchClass = u3ImmOperand; }
|
||||
def u3_0Imm : Operand<i32>;
|
||||
def u3_0Imm : Operand<i32> { let ParserMatchClass = u3_0ImmOperand; }
|
||||
def u3_1Imm : Operand<i32>;
|
||||
def u3_2Imm : Operand<i32>;
|
||||
def u3_3Imm : Operand<i32>;
|
||||
def u2Imm : Operand<i32> { let ParserMatchClass = u2ImmOperand; }
|
||||
def u1Imm : Operand<i32> { let ParserMatchClass = u1ImmOperand; }
|
||||
def n8Imm : Operand<i32> { let ParserMatchClass = n8ImmOperand; }
|
||||
def u2_0Imm : Operand<i32> { let ParserMatchClass = u2_0ImmOperand; }
|
||||
def u1_0Imm : Operand<i32> { let ParserMatchClass = u1_0ImmOperand; }
|
||||
def n8_0Imm : Operand<i32> { let ParserMatchClass = n8_0ImmOperand; }
|
||||
}
|
||||
|
||||
let OperandType = "OPERAND_IMMEDIATE" in {
|
||||
|
|
@ -121,11 +111,6 @@ let OperandType = "OPERAND_IMMEDIATE" in {
|
|||
//
|
||||
// Immediate predicates
|
||||
//
|
||||
def s32ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isInt<32>(v);
|
||||
}]>;
|
||||
|
||||
def s32_0ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isInt<32>(v);
|
||||
|
|
@ -146,22 +131,22 @@ def s29_3ImmPred : PatLeaf<(i32 imm), [{
|
|||
return isShiftedInt<29,3>(v);
|
||||
}]>;
|
||||
|
||||
def s10ImmPred : PatLeaf<(i32 imm), [{
|
||||
def s10_0ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isInt<10>(v);
|
||||
}]>;
|
||||
|
||||
def s8ImmPred : PatLeaf<(i32 imm), [{
|
||||
def s8_0ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isInt<8>(v);
|
||||
}]>;
|
||||
|
||||
def s8Imm64Pred : PatLeaf<(i64 imm), [{
|
||||
def s8_0Imm64Pred : PatLeaf<(i64 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isInt<8>(v);
|
||||
}]>;
|
||||
|
||||
def s6ImmPred : PatLeaf<(i32 imm), [{
|
||||
def s6_0ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isInt<6>(v);
|
||||
}]>;
|
||||
|
|
@ -186,7 +171,7 @@ def s4_3ImmPred : PatLeaf<(i32 imm), [{
|
|||
return isShiftedInt<4,3>(v);
|
||||
}]>;
|
||||
|
||||
def u32ImmPred : PatLeaf<(i32 imm), [{
|
||||
def u32_0ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<32>(v);
|
||||
}]>;
|
||||
|
|
@ -201,27 +186,22 @@ def u11_3ImmPred : PatLeaf<(i32 imm), [{
|
|||
return isShiftedUInt<11,3>(v);
|
||||
}]>;
|
||||
|
||||
def u9ImmPred : PatLeaf<(i32 imm), [{
|
||||
def u9_0ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<9>(v);
|
||||
}]>;
|
||||
|
||||
def u8ImmPred : PatLeaf<(i32 imm), [{
|
||||
def u8_0ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<8>(v);
|
||||
}]>;
|
||||
|
||||
def u7StrictPosImmPred : ImmLeaf<i32, [{
|
||||
// u7StrictPosImmPred predicate - True if the immediate fits in an 7-bit
|
||||
def u7_0StrictPosImmPred : ImmLeaf<i32, [{
|
||||
// u7_0StrictPosImmPred predicate - True if the immediate fits in an 7-bit
|
||||
// unsigned field and is strictly greater than 0.
|
||||
return isUInt<7>(Imm) && Imm > 0;
|
||||
}]>;
|
||||
|
||||
def u6ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<6>(v);
|
||||
}]>;
|
||||
|
||||
def u6_0ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<6>(v);
|
||||
|
|
@ -237,36 +217,36 @@ def u6_2ImmPred : PatLeaf<(i32 imm), [{
|
|||
return isShiftedUInt<6,2>(v);
|
||||
}]>;
|
||||
|
||||
def u5ImmPred : PatLeaf<(i32 imm), [{
|
||||
def u5_0ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<5>(v);
|
||||
}]>;
|
||||
|
||||
def u4ImmPred : PatLeaf<(i32 imm), [{
|
||||
def u4_0ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<4>(v);
|
||||
}]>;
|
||||
|
||||
def u3ImmPred : PatLeaf<(i32 imm), [{
|
||||
def u3_0ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<3>(v);
|
||||
}]>;
|
||||
|
||||
def u2ImmPred : PatLeaf<(i32 imm), [{
|
||||
def u2_0ImmPred : PatLeaf<(i32 imm), [{
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return isUInt<2>(v);
|
||||
}]>;
|
||||
|
||||
def m5ImmPred : PatLeaf<(i32 imm), [{
|
||||
// m5ImmPred predicate - True if the number is in range -1 .. -31
|
||||
def m5_0ImmPred : PatLeaf<(i32 imm), [{
|
||||
// m5_0ImmPred predicate - True if the number is in range -1 .. -31
|
||||
// and will fit in a 5 bit field when made positive, for use in memops.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return (-31 <= v && v <= -1);
|
||||
}]>;
|
||||
|
||||
//InN means negative integers in [-(2^N - 1), 0]
|
||||
def n8ImmPred : PatLeaf<(i32 imm), [{
|
||||
// n8ImmPred predicate - True if the immediate fits in a 8-bit signed
|
||||
def n8_0ImmPred : PatLeaf<(i32 imm), [{
|
||||
// n8_0ImmPred predicate - True if the immediate fits in a 8-bit signed
|
||||
// field.
|
||||
int64_t v = (int64_t)N->getSExtValue();
|
||||
return (-255 <= v && v <= 0);
|
||||
|
|
@ -300,64 +280,62 @@ def Clr5ImmPred : PatLeaf<(i32 imm), [{
|
|||
|
||||
// Extendable immediate operands.
|
||||
def f32ExtOperand : AsmOperandClass { let Name = "f32Ext"; }
|
||||
def s16ExtOperand : AsmOperandClass { let Name = "s16Ext"; }
|
||||
def s12ExtOperand : AsmOperandClass { let Name = "s12Ext"; }
|
||||
def s10ExtOperand : AsmOperandClass { let Name = "s10Ext"; }
|
||||
def s9ExtOperand : AsmOperandClass { let Name = "s9Ext"; }
|
||||
def s8ExtOperand : AsmOperandClass { let Name = "s8Ext"; }
|
||||
def s7ExtOperand : AsmOperandClass { let Name = "s7Ext"; }
|
||||
def s6ExtOperand : AsmOperandClass { let Name = "s6Ext"; }
|
||||
def s16_0ExtOperand : AsmOperandClass { let Name = "s16_0Ext"; }
|
||||
def s12_0ExtOperand : AsmOperandClass { let Name = "s12_0Ext"; }
|
||||
def s10_0ExtOperand : AsmOperandClass { let Name = "s10_0Ext"; }
|
||||
def s9_0ExtOperand : AsmOperandClass { let Name = "s9_0Ext"; }
|
||||
def s8_0ExtOperand : AsmOperandClass { let Name = "s8_0Ext"; }
|
||||
def s7_0ExtOperand : AsmOperandClass { let Name = "s7_0Ext"; }
|
||||
def s6_0ExtOperand : AsmOperandClass { let Name = "s6_0Ext"; }
|
||||
def s11_0ExtOperand : AsmOperandClass { let Name = "s11_0Ext"; }
|
||||
def s11_1ExtOperand : AsmOperandClass { let Name = "s11_1Ext"; }
|
||||
def s11_2ExtOperand : AsmOperandClass { let Name = "s11_2Ext"; }
|
||||
def s11_3ExtOperand : AsmOperandClass { let Name = "s11_3Ext"; }
|
||||
def u6ExtOperand : AsmOperandClass { let Name = "u6Ext"; }
|
||||
def u7ExtOperand : AsmOperandClass { let Name = "u7Ext"; }
|
||||
def u8ExtOperand : AsmOperandClass { let Name = "u8Ext"; }
|
||||
def u9ExtOperand : AsmOperandClass { let Name = "u9Ext"; }
|
||||
def u10ExtOperand : AsmOperandClass { let Name = "u10Ext"; }
|
||||
def u6_0ExtOperand : AsmOperandClass { let Name = "u6_0Ext"; }
|
||||
def u7_0ExtOperand : AsmOperandClass { let Name = "u7_0Ext"; }
|
||||
def u8_0ExtOperand : AsmOperandClass { let Name = "u8_0Ext"; }
|
||||
def u9_0ExtOperand : AsmOperandClass { let Name = "u9_0Ext"; }
|
||||
def u10_0ExtOperand : AsmOperandClass { let Name = "u10_0Ext"; }
|
||||
def u6_1ExtOperand : AsmOperandClass { let Name = "u6_1Ext"; }
|
||||
def u6_2ExtOperand : AsmOperandClass { let Name = "u6_2Ext"; }
|
||||
def u6_3ExtOperand : AsmOperandClass { let Name = "u6_3Ext"; }
|
||||
def u32MustExtOperand : AsmOperandClass { let Name = "u32MustExt"; }
|
||||
def u32_0MustExtOperand : AsmOperandClass { let Name = "u32_0MustExt"; }
|
||||
|
||||
|
||||
|
||||
let OperandType = "OPERAND_IMMEDIATE", PrintMethod = "printExtOperand",
|
||||
DecoderMethod = "unsignedImmDecoder" in {
|
||||
def f32Ext : Operand<f32> { let ParserMatchClass = f32ExtOperand; }
|
||||
def s16Ext : Operand<i32> { let ParserMatchClass = s16ExtOperand;
|
||||
let DecoderMethod = "s16ImmDecoder"; }
|
||||
def s12Ext : Operand<i32> { let ParserMatchClass = s12ExtOperand;
|
||||
let DecoderMethod = "s12ImmDecoder"; }
|
||||
def s16_0Ext : Operand<i32> { let ParserMatchClass = s16_0ExtOperand;
|
||||
let DecoderMethod = "s16_0ImmDecoder"; }
|
||||
def s12_0Ext : Operand<i32> { let ParserMatchClass = s12_0ExtOperand;
|
||||
let DecoderMethod = "s12_0ImmDecoder"; }
|
||||
def s11_0Ext : Operand<i32> { let ParserMatchClass = s11_0ExtOperand;
|
||||
let DecoderMethod = "s11_0ImmDecoder"; }
|
||||
let DecoderMethod = "s11_0ImmDecoder"; }
|
||||
def s11_1Ext : Operand<i32> { let ParserMatchClass = s11_1ExtOperand;
|
||||
let DecoderMethod = "s11_1ImmDecoder"; }
|
||||
let DecoderMethod = "s11_1ImmDecoder"; }
|
||||
def s11_2Ext : Operand<i32> { let ParserMatchClass = s11_2ExtOperand;
|
||||
let DecoderMethod = "s11_2ImmDecoder"; }
|
||||
let DecoderMethod = "s11_2ImmDecoder"; }
|
||||
def s11_3Ext : Operand<i32> { let ParserMatchClass = s11_3ExtOperand;
|
||||
let DecoderMethod = "s11_3ImmDecoder"; }
|
||||
def s10Ext : Operand<i32> { let ParserMatchClass = s10ExtOperand;
|
||||
let DecoderMethod = "s10ImmDecoder"; }
|
||||
def s9Ext : Operand<i32> { let ParserMatchClass = s9ExtOperand;
|
||||
let DecoderMethod = "s90ImmDecoder"; }
|
||||
def s8Ext : Operand<i32> { let ParserMatchClass = s8ExtOperand;
|
||||
let DecoderMethod = "s8ImmDecoder"; }
|
||||
def s7Ext : Operand<i32> { let ParserMatchClass = s7ExtOperand; }
|
||||
def s6Ext : Operand<i32> { let ParserMatchClass = s6ExtOperand;
|
||||
let DecoderMethod = "s6_0ImmDecoder"; }
|
||||
def u6Ext : Operand<i32> { let ParserMatchClass = u6ExtOperand; }
|
||||
def u7Ext : Operand<i32> { let ParserMatchClass = u7ExtOperand; }
|
||||
def u8Ext : Operand<i32> { let ParserMatchClass = u8ExtOperand; }
|
||||
def u9Ext : Operand<i32> { let ParserMatchClass = u9ExtOperand; }
|
||||
def u10Ext : Operand<i32> { let ParserMatchClass = u10ExtOperand; }
|
||||
let DecoderMethod = "s11_3ImmDecoder"; }
|
||||
def s10_0Ext : Operand<i32> { let ParserMatchClass = s10_0ExtOperand;
|
||||
let DecoderMethod = "s10_0ImmDecoder"; }
|
||||
def s9_0Ext : Operand<i32> { let ParserMatchClass = s9_0ExtOperand;
|
||||
let DecoderMethod = "s9_0ImmDecoder"; }
|
||||
def s8_0Ext : Operand<i32> { let ParserMatchClass = s8_0ExtOperand;
|
||||
let DecoderMethod = "s8_0ImmDecoder"; }
|
||||
def s7_0Ext : Operand<i32> { let ParserMatchClass = s7_0ExtOperand; }
|
||||
def s6_0Ext : Operand<i32> { let ParserMatchClass = s6_0ExtOperand;
|
||||
let DecoderMethod = "s6_0ImmDecoder"; }
|
||||
def u7_0Ext : Operand<i32> { let ParserMatchClass = u7_0ExtOperand; }
|
||||
def u8_0Ext : Operand<i32> { let ParserMatchClass = u8_0ExtOperand; }
|
||||
def u9_0Ext : Operand<i32> { let ParserMatchClass = u9_0ExtOperand; }
|
||||
def u10_0Ext : Operand<i32> { let ParserMatchClass = u10_0ExtOperand; }
|
||||
def u6_0Ext : Operand<i32> { let ParserMatchClass = u6_0ExtOperand; }
|
||||
def u6_1Ext : Operand<i32> { let ParserMatchClass = u6_1ExtOperand; }
|
||||
def u6_2Ext : Operand<i32> { let ParserMatchClass = u6_2ExtOperand; }
|
||||
def u6_3Ext : Operand<i32> { let ParserMatchClass = u6_3ExtOperand; }
|
||||
def u32MustExt : Operand<i32> { let ParserMatchClass = u32MustExtOperand; }
|
||||
def u32_0MustExt : Operand<i32> { let ParserMatchClass = u32_0MustExtOperand; }
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -118,7 +118,7 @@ def Y2_isync: JRInst <(outs), (ins),
|
|||
let hasSideEffects = 0, isSolo = 1 in
|
||||
class J2_MISC_TRAP_PAUSE<string mnemonic, bits<2> MajOp>
|
||||
: JRInst
|
||||
<(outs), (ins u8Imm:$u8),
|
||||
<(outs), (ins u8_0Imm:$u8),
|
||||
#mnemonic#"(#$u8)"> {
|
||||
bits<8> u8;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue