forked from OSchip/llvm-project
Generate DBG_VALUE from dbg.value intrinsics. These currently
comes out as comments but will eventually generate DWARF. llvm-svn: 96601
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@ -1161,10 +1161,41 @@ bool X86FastISel::X86VisitIntrinsicCall(IntrinsicInst &I) {
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if (!X86SelectAddress(DI->getAddress(), AM))
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return false;
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const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
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// FIXME may need to add RegState::Debug to any registers produced,
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// although ESP/EBP should be the only ones at the moment.
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addFullAddress(BuildMI(MBB, DL, II), AM).addImm(0).
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addMetadata(DI->getVariable());
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return true;
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}
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case Intrinsic::dbg_value: {
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// FIXME this should eventually be moved to FastISel, when all targets
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// are able to cope with DBG_VALUE. There is nothing target dependent here.
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DbgValueInst *DI = cast<DbgValueInst>(&I);
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const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
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Value *V = DI->getValue();
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if (!V) {
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// Currently the optimizer can produce this; insert an undef to
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// help debugging. Probably the optimizer should not do this.
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BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()).
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addMetadata(DI->getVariable());
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} else if (ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
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BuildMI(MBB, DL, II).addImm(CI->getZExtValue()).addImm(DI->getOffset()).
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addMetadata(DI->getVariable());
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} else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
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BuildMI(MBB, DL, II).addFPImm(CF).addImm(DI->getOffset()).
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addMetadata(DI->getVariable());
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} else if (unsigned Reg = lookUpRegForValue(V)) {
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BuildMI(MBB, DL, II).addReg(Reg, RegState::Debug).addImm(DI->getOffset()).
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addMetadata(DI->getVariable());
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} else {
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// We can't yet handle anything else here because it would require
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// generating code, thus altering codegen because of debug info.
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// Insert an undef so we can see what we dropped.
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BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()).
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addMetadata(DI->getVariable());
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}
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return true;
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}
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case Intrinsic::trap: {
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BuildMI(MBB, DL, TII.get(X86::TRAP));
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return true;
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