forked from OSchip/llvm-project
[ARM] [FIX] Add missing f16 vector operations lowering
Summary: Add missing <8xhalf> shufflevectors pattern, when using concat_vector dag node. As well, allows <8xhalf> and <4xhalf> vldup1 operations. These instructions are required for v8.2a fp16 lowering of vmul_n_f16, vmulq_n_f16 and vmulq_lane_f16 intrinsics. Reviewers: olista01, pbarrio, LukeGeeson, efriedma Reviewed By: efriedma Subscribers: efriedma, javed.absar, kristof.beyls, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60319 llvm-svn: 358081
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48e2eb0b27
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llvm
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@ -2212,7 +2212,10 @@ void ARMDAGToDAGISel::SelectVLDDup(SDNode *N, bool IsIntrinsic,
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case MVT::v8i8:
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case MVT::v16i8: OpcodeIndex = 0; break;
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case MVT::v4i16:
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case MVT::v8i16: OpcodeIndex = 1; break;
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case MVT::v8i16:
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case MVT::v4f16:
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case MVT::v8f16:
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OpcodeIndex = 1; break;
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case MVT::v2f32:
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case MVT::v2i32:
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case MVT::v4f32:
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@ -7576,6 +7576,8 @@ def : Pat<(v16i8 (concat_vectors DPR:$Dn, DPR:$Dm)),
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(REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>;
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def : Pat<(v4f32 (concat_vectors DPR:$Dn, DPR:$Dm)),
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(REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>;
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def : Pat<(v8f16 (concat_vectors DPR:$Dn, DPR:$Dm)),
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(REG_SEQUENCE QPR, DPR:$Dn, dsub_0, DPR:$Dm, dsub_1)>;
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//===----------------------------------------------------------------------===//
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// Assembler aliases
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@ -1225,6 +1225,42 @@ entry:
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ret <8 x half> %shuffle.i
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}
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define <4 x half> @test_vld_dup1_4xhalf(half* %b) {
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; CHECK-LABEL: test_vld_dup1_4xhalf:
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; CHECK: vld1.16 {d0[]}, [r0:16]
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; CHECK-NEXT: bx lr
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entry:
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%b1 = load half, half* %b, align 2
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%vecinit = insertelement <4 x half> undef, half %b1, i32 0
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%vecinit2 = insertelement <4 x half> %vecinit, half %b1, i32 1
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%vecinit3 = insertelement <4 x half> %vecinit2, half %b1, i32 2
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%vecinit4 = insertelement <4 x half> %vecinit3, half %b1, i32 3
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ret <4 x half> %vecinit4
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}
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define <8 x half> @test_vld_dup1_8xhalf(half* %b) local_unnamed_addr {
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; CHECK-LABEL: test_vld_dup1_8xhalf:
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; CHECK: vld1.16 {d0[], d1[]}, [r0:16]
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; CHECK-NEXT: bx lr
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entry:
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%b1 = load half, half* %b, align 2
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%vecinit = insertelement <8 x half> undef, half %b1, i32 0
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%vecinit8 = shufflevector <8 x half> %vecinit, <8 x half> undef, <8 x i32> zeroinitializer
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ret <8 x half> %vecinit8
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}
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define <8 x half> @test_shufflevector8xhalf(<4 x half> %a) {
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; CHECK-LABEL: test_shufflevector8xhalf:
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; CHECK: vmov.f64 d1, d0
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; CHECK-NEXT: bx lr
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entry:
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%r = shufflevector <4 x half> %a, <4 x half> %a, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x half> %r
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}
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declare <4 x half> @llvm.fabs.v4f16(<4 x half>)
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declare <8 x half> @llvm.fabs.v8f16(<8 x half>)
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declare <4 x i16> @llvm.arm.neon.vcvtas.v4i16.v4f16(<4 x half>)
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