Comment from code review

llvm-svn: 151178

llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

@@ -362,6 +362,7 @@ void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) {
   unsigned Reg = MI->getOperand(OperIdx).getReg();
 
   // SSA defs do not have output/anti dependencies.
+  // The current operand is a def, so we have at least one.
   if (llvm::next(MRI.def_begin(Reg)) == MRI.def_end())
     return;