forked from OSchip/llvm-project
[DAGCombiner] Fold vecreduce_or/and if operand is insert_subvector.
Fold: vecreduce_or(insert_subvec(zeroinitializer, vec)) -> vecreduce_or(vec) vecreduce_and(insert_subvec(allones, vec)) -> vecreduce_and(vec) vecreduce_and/or(insert_subvec(undef, vec)) -> vecreduce_and/or(vec) This is useful for SVE which uses insert/extract subvector to convert fixed-width to/from scalable vectors. Reviewed By: bsmith Differential Revision: https://reviews.llvm.org/D118919
This commit is contained in:
Sander de Smalen
parent
bec1aa3069
commit
6452549f30
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@ -22519,6 +22519,19 @@ SDValue DAGCombiner::visitVECREDUCE(SDNode *N) {
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return DAG.getNode(NewOpcode, SDLoc(N), N->getValueType(0), N0);
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}
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// vecreduce_or(insert_subvector(zero or undef, val)) -> vecreduce_or(val)
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// vecreduce_and(insert_subvector(ones or undef, val)) -> vecreduce_and(val)
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if (N0.getOpcode() == ISD::INSERT_SUBVECTOR &&
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TLI.isTypeLegal(N0.getOperand(1).getValueType())) {
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SDValue Vec = N0.getOperand(0);
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SDValue Subvec = N0.getOperand(1);
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if ((Opcode == ISD::VECREDUCE_OR &&
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(N0.getOperand(0).isUndef() || isNullOrNullSplat(Vec))) ||
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(Opcode == ISD::VECREDUCE_AND &&
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(N0.getOperand(0).isUndef() || isAllOnesOrAllOnesSplat(Vec))))
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return DAG.getNode(Opcode, SDLoc(N), N->getValueType(0), Subvec);
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}
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return SDValue();
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}
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@ -0,0 +1,98 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64 -mattr=+sve < %s | FileCheck %s
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;
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; OR reductions
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;
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define i1 @reduce_or_insert_subvec_into_zero(<vscale x 4 x i1> %in) {
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; CHECK-LABEL: reduce_or_insert_subvec_into_zero:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptest p0, p0.b
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%t = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> zeroinitializer, <vscale x 4 x i1> %in, i64 0)
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%res = call i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1> %t)
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ret i1 %res
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}
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define i1 @reduce_or_insert_subvec_into_poison(<vscale x 4 x i1> %in) {
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; CHECK-LABEL: reduce_or_insert_subvec_into_poison:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptest p0, p0.b
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%t = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> poison, <vscale x 4 x i1> %in, i64 0)
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%res = call i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1> %t)
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ret i1 %res
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}
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define i1 @reduce_or_insert_subvec_into_nonzero(<vscale x 4 x i1> %in, <vscale x 16 x i1> %vec) {
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; CHECK-LABEL: reduce_or_insert_subvec_into_nonzero:
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; CHECK: // %bb.0:
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; CHECK-NEXT: punpklo p2.h, p1.b
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; CHECK-NEXT: punpkhi p1.h, p1.b
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; CHECK-NEXT: punpkhi p2.h, p2.b
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; CHECK-NEXT: uzp1 p0.h, p0.h, p2.h
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; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b
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; CHECK-NEXT: ptest p0, p0.b
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; CHECK-NEXT: cset w0, ne
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; CHECK-NEXT: ret
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%t = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %in, i64 0)
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%res = call i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1> %t)
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ret i1 %res
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}
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;
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; AND reductions
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;
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define i1 @reduce_and_insert_subvec_into_ones(<vscale x 4 x i1> %in) {
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; CHECK-LABEL: reduce_and_insert_subvec_into_ones:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p1.s
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; CHECK-NEXT: not p0.b, p1/z, p0.b
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; CHECK-NEXT: ptest p1, p0.b
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%allones.ins = insertelement <vscale x 16 x i1> poison, i1 1, i32 0
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%allones = shufflevector <vscale x 16 x i1> %allones.ins, <vscale x 16 x i1> poison, <vscale x 16 x i32> zeroinitializer
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%t = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> %allones, <vscale x 4 x i1> %in, i64 0)
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%res = call i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1> %t)
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ret i1 %res
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}
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define i1 @reduce_and_insert_subvec_into_poison(<vscale x 4 x i1> %in) {
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; CHECK-LABEL: reduce_and_insert_subvec_into_poison:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p1.s
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; CHECK-NEXT: not p0.b, p1/z, p0.b
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; CHECK-NEXT: ptest p1, p0.b
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%t = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> poison, <vscale x 4 x i1> %in, i64 0)
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%res = call i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1> %t)
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ret i1 %res
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}
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define i1 @reduce_and_insert_subvec_into_var(<vscale x 4 x i1> %in, <vscale x 16 x i1> %vec) {
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; CHECK-LABEL: reduce_and_insert_subvec_into_var:
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; CHECK: // %bb.0:
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; CHECK-NEXT: punpklo p3.h, p1.b
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; CHECK-NEXT: punpkhi p1.h, p1.b
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; CHECK-NEXT: punpkhi p3.h, p3.b
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; CHECK-NEXT: ptrue p2.b
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; CHECK-NEXT: uzp1 p0.h, p0.h, p3.h
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; CHECK-NEXT: uzp1 p0.b, p0.b, p1.b
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; CHECK-NEXT: not p0.b, p2/z, p0.b
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; CHECK-NEXT: ptest p2, p0.b
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; CHECK-NEXT: cset w0, eq
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; CHECK-NEXT: ret
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%t = call <vscale x 16 x i1> @llvm.experimental.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1> %vec, <vscale x 4 x i1> %in, i64 0)
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%res = call i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1> %t)
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ret i1 %res
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}
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declare i1 @llvm.vector.reduce.and.nxv16i1(<vscale x 16 x i1>)
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declare i1 @llvm.vector.reduce.or.nxv16i1(<vscale x 16 x i1>)
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declare <vscale x 16 x i1> @llvm.experimental.vector.insert.nxv16i1.nxv4i1(<vscale x 16 x i1>, <vscale x 4 x i1>, i64)
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