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Teach SimplifySetCC that comparing AssertZext i1 against a constant 1 can be rewritten as a compare against a constant 0 with the opposite condition. 

llvm-svn: 170495
This commit is contained in:
Craig Topper 2012-12-19 06:12:28 +00:00
parent 3aad762d1d
commit 63f5921776
2 changed files with 24 additions and 3 deletions
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12
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -2206,9 +2206,10 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ; Cond = (Cond == ISD::SETEQ) ? ISD::SETNE : ISD::SETEQ;
return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1), return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
Cond); Cond);
} else if (Op0.getOpcode() == ISD::AND && }
isa<ConstantSDNode>(Op0.getOperand(1)) && if (Op0.getOpcode() == ISD::AND &&
cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) { isa<ConstantSDNode>(Op0.getOperand(1)) &&
cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
// If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
if (Op0.getValueType().bitsGT(VT)) if (Op0.getValueType().bitsGT(VT))
Op0 = DAG.getNode(ISD::AND, dl, VT, Op0 = DAG.getNode(ISD::AND, dl, VT,
@ -2223,6 +2224,11 @@ TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
DAG.getConstant(0, Op0.getValueType()), DAG.getConstant(0, Op0.getValueType()),
Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ); Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
} }
if (Op0.getOpcode() == ISD::AssertZext &&
cast<VTSDNode>(Op0.getOperand(1))->getVT() == MVT::i1)
return DAG.getSetCC(dl, VT, Op0,
DAG.getConstant(0, Op0.getValueType()),
Cond == ISD::SETEQ ? ISD::SETNE : ISD::SETEQ);
} }
} }

15
llvm/test/CodeGen/X86/cmp.ll
View File

@ -151,3 +151,18 @@ entry:
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i32 @test12() uwtable ssp {
; CHECK: test12:
; CHECK: testb
%1 = call zeroext i1 @test12b()
br i1 %1, label %2, label %3
; <label>:2 ; preds = %0
ret i32 1
; <label>:3 ; preds = %0
ret i32 2
}
declare zeroext i1 @test12b()