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[RISCV] Compress addiw rd, x0, simm6 to c.li rd, simm6 

A pattern was present for addi rd, x0, simm6 but not addiw which is
semantically identical when the source register is x0. This patch addresses
that, and the benefit can be seen in rv64c-aliases-valid.s.

llvm-svn: 343911
This commit is contained in:
Alex Bradbury 2018-10-06 06:09:46 +00:00
parent 251ee083a3
commit 639df9e4c0
2 changed files with 12 additions and 10 deletions
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2
llvm/lib/Target/RISCV/RISCVInstrInfoC.td
View File

@ -625,6 +625,8 @@ def : CompressPat<(AND GPRC:$rs1, GPRC:$rs2, GPRC:$rs1),
} // Predicates = [HasStdExtC]
let Predicates = [HasStdExtC, IsRV64] in {
def : CompressPat<(ADDIW GPRNoX0:$rd, X0, simm6:$imm),
(C_LI GPRNoX0:$rd, simm6:$imm)>;
def : CompressPat<(SUBW GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),
(C_SUBW GPRC:$rs1, GPRC:$rs2)>;
def : CompressPat<(ADDW GPRC:$rs1, GPRC:$rs1, GPRC:$rs2),

20
llvm/test/MC/RISCV/rv64c-aliases-valid.s
View File

@ -8,11 +8,11 @@
# CHECK-INST.....Match the canonical instr (tests alias to instr. mapping)
# CHECK-EXPAND...Match canonical instr. unconditionally (tests alias expansion)
# CHECK-EXPAND: addiw a0, zero, 0
# CHECK-EXPAND: c.li a0, 0
li x10, 0
# CHECK-EXPAND: addiw a0, zero, 1
# CHECK-EXPAND: c.li a0, 1
li x10, 1
# CHECK-EXPAND: addiw a0, zero, -1
# CHECK-EXPAND: c.li a0, -1
li x10, -1
# CHECK-EXPAND: addiw a0, zero, 2047
li x10, 2047
@ -56,28 +56,28 @@ li x12, -2147483648
# CHECK-EXPAND: lui a2, 524288
li x12, -0x80000000
# CHECK-EXPAND: addiw a2, zero, 1
# CHECK-EXPAND: c.li a2, 1
# CHECK-EXPAND: c.slli a2, 31
li x12, 0x80000000
# CHECK-EXPAND: addiw a2, zero, 1
# CHECK-EXPAND: c.li a2, 1
# CHECK-EXPAND: c.slli a2, 32
# CHECK-EXPAND: c.addi a2, -1
li x12, 0xFFFFFFFF
# CHECK-EXPAND: addiw t0, zero, 1
# CHECK-EXPAND: c.li t0, 1
# CHECK-EXPAND: c.slli t0, 32
li t0, 0x100000000
# CHECK-EXPAND: addiw t1, zero, -1
# CHECK-EXPAND: c.li t1, -1
# CHECK-EXPAND: c.slli t1, 63
li t1, 0x8000000000000000
# CHECK-EXPAND: addiw t1, zero, -1
# CHECK-EXPAND: c.li t1, -1
# CHECK-EXPAND: c.slli t1, 63
li t1, -0x8000000000000000
# CHECK-EXPAND: lui t2, 9321
# CHECK-EXPAND: addiw t2, t2, -1329
# CHECK-EXPAND: c.slli t2, 35
li t2, 0x1234567800000000
# CHECK-EXPAND: addiw t3, zero, 7
# CHECK-EXPAND: c.li t3, 7
# CHECK-EXPAND: c.slli t3, 36
# CHECK-EXPAND: c.addi t3, 11
# CHECK-EXPAND: c.slli t3, 24
@ -92,5 +92,5 @@ li t3, 0x700000000B00000F
# CHECK-EXPAND: c.slli t4, 13
# CHECK-EXPAND: addi t4, t4, -272
li t4, 0x123456789abcdef0
# CHECK-EXPAND: addiw t5, zero, -1
# CHECK-EXPAND: c.li t5, -1
li t5, 0xFFFFFFFFFFFFFFFF