forked from OSchip/llvm-project
[ARM,MVE] Add vbrsrq intrinsics family
Summary: This patch adds a new MVE intrinsics family, `vbrsrq`: vector bit reverse and shift right. The intrinsics are compiled into the VBRSR instruction. Two new LLVM IR intrinsics were also added: arm.mve.vbrsr and arm.mve.vbrsr.predicated. Reviewers: simon_tatham, dmgreen, ostannard, MarkMurrayARM Reviewed By: simon_tatham Subscribers: kristof.beyls, hiraditya, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D74721
This commit is contained in:
Mikhail Maltsev
parent
e32522ca17
commit
63809d365e
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@ -1276,3 +1276,13 @@ foreach desttype = !listconcat(T.Int16, T.Int32, T.Float) in {
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1, "_n_"#desttype, PNT_2Type, pnt_nx>;
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}
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}
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let params = T.All in {
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let pnt = PNT_NType in
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def vbrsrq_n: Intrinsic<Vector, (args Vector:$a, s32:$b),
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(IRInt<"vbrsr", [Vector]> $a, $b)>;
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defm vbrsrq : IntrinsicMX<Vector, (args Vector:$a, s32:$b, Predicate:$pred),
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(IRInt<"vbrsr_predicated", [Vector, Predicate]>
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$inactive, $a, $b, $pred), 1, "_n",
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PNT_NType, PNT_NType>;
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}
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@ -0,0 +1,92 @@
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// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
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// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
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#include <arm_mve.h>
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// CHECK-LABEL: @test_vbrsrq_n_u32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32> [[A:%.*]], i32 [[B:%.*]])
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// CHECK-NEXT: ret <4 x i32> [[TMP0]]
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//
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uint32x4_t test_vbrsrq_n_u32(uint32x4_t a, int32_t b) {
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#ifdef POLYMORPHIC
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return vbrsrq(a, b);
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#else /* POLYMORPHIC */
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return vbrsrq_n_u32(a, b);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vbrsrq_n_f16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half> [[A:%.*]], i32 [[B:%.*]])
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// CHECK-NEXT: ret <8 x half> [[TMP0]]
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//
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float16x8_t test_vbrsrq_n_f16(float16x8_t a, int32_t b) {
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#ifdef POLYMORPHIC
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return vbrsrq(a, b);
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#else /* POLYMORPHIC */
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return vbrsrq_n_f16(a, b);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vbrsrq_m_n_s8(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
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// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8> [[INACTIVE:%.*]], <16 x i8> [[A:%.*]], i32 [[B:%.*]], <16 x i1> [[TMP1]])
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// CHECK-NEXT: ret <16 x i8> [[TMP2]]
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//
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int8x16_t test_vbrsrq_m_n_s8(int8x16_t inactive, int8x16_t a, int32_t b, mve_pred16_t p) {
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#ifdef POLYMORPHIC
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return vbrsrq_m(inactive, a, b, p);
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#else /* POLYMORPHIC */
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return vbrsrq_m_n_s8(inactive, a, b, p);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vbrsrq_m_n_f32(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
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// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float> [[INACTIVE:%.*]], <4 x float> [[A:%.*]], i32 [[B:%.*]], <4 x i1> [[TMP1]])
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// CHECK-NEXT: ret <4 x float> [[TMP2]]
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//
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float32x4_t test_vbrsrq_m_n_f32(float32x4_t inactive, float32x4_t a, int32_t b, mve_pred16_t p) {
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#ifdef POLYMORPHIC
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return vbrsrq_m(inactive, a, b, p);
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#else /* POLYMORPHIC */
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return vbrsrq_m_n_f32(inactive, a, b, p);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vbrsrq_x_n_u16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
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// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16> undef, <8 x i16> [[A:%.*]], i32 [[B:%.*]], <8 x i1> [[TMP1]])
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// CHECK-NEXT: ret <8 x i16> [[TMP2]]
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//
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uint16x8_t test_vbrsrq_x_n_u16(uint16x8_t a, int32_t b, mve_pred16_t p) {
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#ifdef POLYMORPHIC
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return vbrsrq_x(a, b, p);
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#else /* POLYMORPHIC */
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return vbrsrq_x_n_u16(a, b, p);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @test_vbrsrq_x_n_f16(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
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// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half> undef, <8 x half> [[A:%.*]], i32 [[B:%.*]], <8 x i1> [[TMP1]])
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// CHECK-NEXT: ret <8 x half> [[TMP2]]
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//
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float16x8_t test_vbrsrq_x_n_f16(float16x8_t a, int32_t b, mve_pred16_t p) {
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#ifdef POLYMORPHIC
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return vbrsrq_x(a, b, p);
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#else /* POLYMORPHIC */
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return vbrsrq_x_n_f16(a, b, p);
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#endif /* POLYMORPHIC */
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}
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@ -1164,4 +1164,8 @@ def int_arm_mve_vrintn: Intrinsic<
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def int_arm_mve_vcls: Intrinsic<
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[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
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defm int_arm_mve_vbrsr: MVEMXPredicated<
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[llvm_anyvector_ty], [],
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[LLVMMatchType<0>, llvm_i32_ty], LLVMMatchType<0>, llvm_anyvector_ty>;
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} // end TargetPrefix
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@ -4795,6 +4795,20 @@ def MVE_VBRSR8 : MVE_VBRSR<"vbrsr", "8", 0b00>;
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def MVE_VBRSR16 : MVE_VBRSR<"vbrsr", "16", 0b01>;
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def MVE_VBRSR32 : MVE_VBRSR<"vbrsr", "32", 0b10>;
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multiclass MVE_VBRSR_pat_m<MVEVectorVTInfo VTI, Instruction Inst> {
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// Unpredicated
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def : Pat<(VTI.Vec (int_arm_mve_vbrsr (VTI.Vec MQPR:$Qn), (i32 rGPR:$Rm))),
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(VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (i32 rGPR:$Rm)))>;
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// Predicated
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def : Pat<(VTI.Vec (int_arm_mve_vbrsr_predicated
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(VTI.Vec MQPR:$inactive),
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(VTI.Vec MQPR:$Qn), (i32 rGPR:$Rm),
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(VTI.Pred VCCR:$mask))),
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(VTI.Vec (Inst (VTI.Vec MQPR:$Qn), (i32 rGPR:$Rm),
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ARMVCCThen, (VTI.Pred VCCR:$mask),
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(VTI.Vec MQPR:$inactive)))>;
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}
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let Predicates = [HasMVEInt] in {
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def : Pat<(v16i8 ( bitreverse (v16i8 MQPR:$val1))),
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(v16i8 ( MVE_VBRSR8 (v16i8 MQPR:$val1), (t2MOVi (i32 8)) ))>;
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@ -4804,6 +4818,15 @@ let Predicates = [HasMVEInt] in {
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def : Pat<(v8i16 ( bitreverse (v8i16 MQPR:$val1))),
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(v8i16 ( MVE_VBRSR16 (v8i16 MQPR:$val1), (t2MOVi (i32 16)) ))>;
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defm : MVE_VBRSR_pat_m<MVE_v16i8, MVE_VBRSR8>;
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defm : MVE_VBRSR_pat_m<MVE_v8i16, MVE_VBRSR16>;
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defm : MVE_VBRSR_pat_m<MVE_v4i32, MVE_VBRSR32>;
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}
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let Predicates = [HasMVEFloat] in {
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defm : MVE_VBRSR_pat_m<MVE_v8f16, MVE_VBRSR16>;
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defm : MVE_VBRSR_pat_m<MVE_v4f32, MVE_VBRSR32>;
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}
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class MVE_VMUL_qr_int<string iname, string suffix, bits<2> size>
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@ -0,0 +1,89 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
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declare <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half>, i32)
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declare <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32>, i32)
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declare <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>)
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declare <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>)
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declare <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float>, <4 x float>, i32, <4 x i1>)
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declare <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half>, <8 x half>, i32, <8 x i1>)
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declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)
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declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)
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declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
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define arm_aapcs_vfpcc <4 x i32> @test_vbrsrq_n_u32(<4 x i32> %a, i32 %b) {
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; CHECK-LABEL: test_vbrsrq_n_u32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vbrsr.32 q0, q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <4 x i32> @llvm.arm.mve.vbrsr.v4i32(<4 x i32> %a, i32 %b)
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ret <4 x i32> %0
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}
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define arm_aapcs_vfpcc <8 x half> @test_vbrsrq_n_f16(<8 x half> %a, i32 %b) {
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; CHECK-LABEL: test_vbrsrq_n_f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vbrsr.16 q0, q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = call <8 x half> @llvm.arm.mve.vbrsr.v8f16(<8 x half> %a, i32 %b)
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ret <8 x half> %0
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}
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define arm_aapcs_vfpcc <16 x i8> @test_vbrsrq_m_n_s8(<16 x i8> %inactive, <16 x i8> %a, i32 %b, i16 zeroext %p) {
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; CHECK-LABEL: test_vbrsrq_m_n_s8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vbrsrt.8 q0, q1, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
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%2 = call <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8> %inactive, <16 x i8> %a, i32 %b, <16 x i1> %1)
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ret <16 x i8> %2
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}
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define arm_aapcs_vfpcc <4 x float> @test_vbrsrq_m_n_f32(<4 x float> %inactive, <4 x float> %a, i32 %b, i16 zeroext %p) {
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; CHECK-LABEL: test_vbrsrq_m_n_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vbrsrt.32 q0, q1, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
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%2 = call <4 x float> @llvm.arm.mve.vbrsr.predicated.v4f32.v4i1(<4 x float> %inactive, <4 x float> %a, i32 %b, <4 x i1> %1)
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ret <4 x float> %2
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}
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define arm_aapcs_vfpcc <8 x i16> @test_vbrsrq_x_n_u16(<8 x i16> %a, i32 %b, i16 zeroext %p) {
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; CHECK-LABEL: test_vbrsrq_x_n_u16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vbrsrt.16 q0, q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
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%2 = call <8 x i16> @llvm.arm.mve.vbrsr.predicated.v8i16.v8i1(<8 x i16> undef, <8 x i16> %a, i32 %b, <8 x i1> %1)
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ret <8 x i16> %2
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}
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define arm_aapcs_vfpcc <8 x half> @test_vbrsrq_x_n_f16(<8 x half> %a, i32 %b, i16 zeroext %p) {
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; CHECK-LABEL: test_vbrsrq_x_n_f16:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vbrsrt.16 q0, q0, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = zext i16 %p to i32
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%1 = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
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%2 = call <8 x half> @llvm.arm.mve.vbrsr.predicated.v8f16.v8i1(<8 x half> undef, <8 x half> %a, i32 %b, <8 x i1> %1)
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ret <8 x half> %2
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}
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