forked from OSchip/llvm-project
CodeGen: Define Swift's legal vector types for AArch64, ARM
rdar://32401301 llvm-svn: 304017
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@ -4821,6 +4821,9 @@ private:
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bool isSwiftErrorInRegister() const override {
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return true;
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}
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bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy,
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unsigned elts) const override;
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};
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class AArch64TargetCodeGenInfo : public TargetCodeGenInfo {
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@ -4994,6 +4997,17 @@ bool AArch64ABIInfo::isIllegalVectorType(QualType Ty) const {
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return false;
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}
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bool AArch64ABIInfo::isLegalVectorTypeForSwift(CharUnits totalSize,
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llvm::Type *eltTy,
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unsigned elts) const {
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if (!llvm::isPowerOf2_32(elts))
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return false;
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if (totalSize.getQuantity() != 8 &&
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(totalSize.getQuantity() != 16 || elts == 1))
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return false;
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return true;
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}
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bool AArch64ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
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// Homogeneous aggregates for AAPCS64 must have base types of a floating
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// point type or a short-vector type. This is the same as the 32-bit ABI,
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@ -5382,6 +5396,8 @@ private:
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bool isSwiftErrorInRegister() const override {
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return true;
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}
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bool isLegalVectorTypeForSwift(CharUnits totalSize, llvm::Type *eltTy,
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unsigned elts) const override;
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};
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class ARMTargetCodeGenInfo : public TargetCodeGenInfo {
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@ -5894,6 +5910,20 @@ bool ARMABIInfo::isIllegalVectorType(QualType Ty) const {
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return false;
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}
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bool ARMABIInfo::isLegalVectorTypeForSwift(CharUnits vectorSize,
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llvm::Type *eltTy,
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unsigned numElts) const {
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if (!llvm::isPowerOf2_32(numElts))
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return false;
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unsigned size = getDataLayout().getTypeStoreSizeInBits(eltTy);
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if (size > 64)
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return false;
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if (vectorSize.getQuantity() != 8 &&
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(vectorSize.getQuantity() != 16 || numElts == 1))
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return false;
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return true;
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}
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bool ARMABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const {
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// Homogeneous aggregates for AAPCS-VFP must have base types of float,
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// double, or 64-bit or 128-bit vectors.
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@ -1,5 +1,6 @@
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// RUN: %clang_cc1 -triple x86_64-apple-darwin10 -target-cpu core2 -emit-llvm -o - %s | FileCheck %s
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// RUN: %clang_cc1 -triple arm64-apple-ios9 -target-cpu cyclone -emit-llvm -o - %s | FileCheck %s
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// RUN: %clang_cc1 -triple arm64-apple-ios9 -target-cpu cyclone -emit-llvm -o - %s | FileCheck %s --check-prefix=ARM64
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// REQUIRES: aarch64-registered-target,x86-registered-target
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@ -60,6 +61,7 @@ SWIFTCALL void context_error_2(short s, CONTEXT int *self, ERROR float **error)
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/********************************** LOWERING *********************************/
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/*****************************************************************************/
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typedef float float3 __attribute__((ext_vector_type(3)));
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typedef float float4 __attribute__((ext_vector_type(4)));
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typedef float float8 __attribute__((ext_vector_type(8)));
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typedef double double2 __attribute__((ext_vector_type(2)));
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@ -1005,3 +1007,10 @@ struct {
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TEST(union_het_vecint)
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// CHECK: define swiftcc void @return_union_het_vecint([[UNION:%.*]]* noalias sret
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// CHECK: define swiftcc void @take_union_het_vecint([[UNION]]*
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typedef struct {
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float3 f3;
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} struct_v1f3;
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TEST(struct_v1f3)
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// ARM64-LABEL: define swiftcc { <2 x float>, float } @return_struct_v1f3()
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// ARM64-LABEL: define swiftcc void @take_struct_v1f3(<2 x float>, float)
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@ -57,6 +57,7 @@ SWIFTCALL void context_error_2(short s, CONTEXT int *self, ERROR float **error)
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/********************************** LOWERING *********************************/
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/*****************************************************************************/
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typedef float float3 __attribute__((ext_vector_type(3)));
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typedef float float4 __attribute__((ext_vector_type(4)));
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typedef float float8 __attribute__((ext_vector_type(8)));
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typedef double double2 __attribute__((ext_vector_type(2)));
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@ -1013,3 +1014,10 @@ typedef struct {
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TEST(struct_vf81)
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// CHECK-LABEL: define swiftcc { <4 x float>, <4 x float> } @return_struct_vf81()
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// CHECK-LABEL: define swiftcc void @take_struct_vf81(<4 x float>, <4 x float>)
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typedef struct {
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float3 f3;
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} struct_v1f3;
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TEST(struct_v1f3)
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// CHECK-LABEL: define swiftcc { <2 x float>, float } @return_struct_v1f3()
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// CHECK-LABEL: define swiftcc void @take_struct_v1f3(<2 x float>, float)
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