forked from OSchip/llvm-project
[x86] use getSignBit() for clarity; NFCI
llvm-svn: 294333
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@ -29477,8 +29477,8 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
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// If this is a *dynamic* select (non-constant condition) and we can match
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// this node with one of the variable blend instructions, restructure the
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// condition so that the blends can use the high bit of each element and use
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// SimplifyDemandedBits to simplify the condition operand.
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// condition so that blends can use the high (sign) bit of each element and
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// use SimplifyDemandedBits to simplify the condition operand.
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if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
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!DCI.isBeforeLegalize() &&
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!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
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@ -29513,8 +29513,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
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return SDValue();
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assert(BitWidth >= 8 && BitWidth <= 64 && "Invalid mask size");
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APInt DemandedMask = APInt::getHighBitsSet(BitWidth, 1);
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APInt DemandedMask(APInt::getSignBit(BitWidth));
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APInt KnownZero, KnownOne;
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TargetLowering::TargetLoweringOpt TLO(DAG, DCI.isBeforeLegalize(),
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DCI.isBeforeLegalizeOps());
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